Inventor
DHURIA AMIT
US12 patents
Patents
12 patentsUS8863052B1Oct 14, 2014
System and method for generating and using a structurally aware timing model for representative operation of a circuit design
CADENCE DESIGN SYSTEMS INC44 citations93
US8788995B1Jul 22, 2014
System and method for guiding remedial transformations of a circuit design defined by physical implementation data to reduce needed physical corrections for detected timing violations in the circuit design
CADENCE DESIGN SYSTEMS INC55 citations93
US10169501B1Jan 1, 2019
Timing context generation with multi-instance blocks for hierarchical analysis
CADENCE DESIGN SYSTEMS INC7 citations82
US10037394B1Jul 31, 2018
Hierarchical timing analysis for multi-instance blocks
CADENCE DESIGN SYSTEMS INC8 citations82
US10990733B1Apr 27, 2021
Shared timing graph propagation for multi-mode multi-corner static timing analysis
CADENCE DESIGN SYSTEMS INC8 citations81
US9529962B1Dec 27, 2016
System and method for generating and using sibling nets model for shared delay calculation across multi-instantiated blocks in the circuit design
CADENCE DESIGN SYSTEMS INC6 citations71
US9405882B1Aug 2, 2016
High performance static timing analysis system and method for input/output interfaces
CADENCE DESIGN SYSTEMS INC6 citations69
US11003821B1May 11, 2021
Deterministic loop breaking in multi-mode multi-corner static timing analysis of integrated circuits
CADENCE DESIGN SYSTEMS INC6 citations68
US10133842B1Nov 20, 2018
Methods, systems, and articles of manufacture for multi-mode, multi-corner physical optimization of electronic designs
CADENCE DESIGN SYSTEMS INC4 citations68
US11144698B1Oct 12, 2021
Method, system, and product for an improved approach to placement and optimization in a physical design flow
CADENCE DESIGN SYSTEMS INC2 citations66
US11188696B1Nov 30, 2021
Method, system, and product for deferred merge based method for graph based analysis pessimism reduction
CADENCE DESIGN SYSTEMS INC1 citations56
US12475286B1Nov 18, 2025
System and method for comparing circuit design constraint sets
CADENCE DESIGN SYSTEMS INC0 citations40