Inventor

FONTANA FABIANO

US31 patents

⚠️ This page may combine multiple inventors who share the name “FONTANA FABIANO”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

FONTANA FABIANO

LATTICE SEMICONDUCTOR CORP

Enhanced CPLD macrocell module having selectable bypass of steering-based resource allocation and methods of use

Flexible memory architectures for programmable logic devices

Programmable logic device providing a serial peripheral interface

Zero-power programmable memory cell

Enhanced CPLD macrocell module having selectable bypass of steering-based resource allocation

Flexible memory architectures for programmable logic devices

Programmable logic devices with custom identification systems and methods

Programmable logic devices with transparent field reconfiguration

Dual-port SRAM with bit line clamping

Bitline floating circuit for memory power reduction

Programmable logic devices with custom identification systems and methods

Programmable logic devices with user non-volatile memory

Zero-power logic cell for use in programmable logic devices

Flash memory erase verification systems and methods

Flash memory erase verification systems and methods

Power management for integrated circuits such as programmable logic devices

Power management systems and methods for programmable logic devices

Zero-power programmable memory cell

ADVANCED MICRO DEVICES INC

High speed CMOS output buffer circuit minimizes propagation delay and crowbar current

Enhanced method of testing semiconductor devices having nonvolatile elements

Input buffer for a high density programmable logic device

Output buffer for a high density programmable logic device

High speed NOR gate with small output voltage swings

CMOS logic gate clamping circuit

High-speed sense amplifier with regulated feedback

Input buffer circuit with improved speed performance

Sense amplifier and or gate for a high density programmable logic device

Array cell circuit with split read/write line

VANTIS CORP

Phase locked loop with a lock detector

SHARPE-GEISLER BRAD

Dual-port SRAM with bit line clamping

POLLACHEK ROBERT GARY

Voltage discharge circuit having divided discharge current