Inventor

HRUSECKY DAVID A

US50 patents

⚠️ This page may combine multiple inventors who share the name “HRUSECKY DAVID A”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

HRUSECKY DAVID A

IBM

Anti-flicker logic for MPEG video decoder with integrated scaling and display functions

Multi-format reduced memory video decoder with adjustable polyphase expansion filter

MPEG video decoder with integrated scaling and display functions

Color mapped and direct color OSD region processor with support for 4:2:2 profile decode function

Digital video decode system with OSD processor for converting graphics data in 4:4:4 format to 4:2:2 format by mathematically combining chrominance values

System for creating multiple scaled videos from encoded video sources

Arithmetic unit for performing XY+B operation

MPEG video decoder with integrated scaling and display functions

Anti-flicker system for multi-plane graphics

Low latency video decoder with high-quality, variable scaling and minimal frame buffer memory

Operation of a multi-slice processor implementing a load/store unit maintaining rejected instructions

Operation of a multi-slice processor implementing a load/store unit maintaining rejected instructions

Operation of a multi-slice processor with an expanded merge fetching queue

Operation of a multi-slice processor preventing early dependent instruction wakeup

Operation of a multi-slice processor implementing simultaneous two-target loads and stores

Operation of a multi-slice processor implementing simultaneous two-target loads and stores

High performance array multiplier using four-to-two composite counters

Accelerated validity response permitting early issue of instructions dependent upon outcome of floating point operations

Virtual cache mechanism for program break point register exception handling

Handling unaligned load operations in a multi-slice computer processor

Handling unaligned load operations in a multi-slice computer processor

Managing a divided load reorder queue

Color mapped and direct color OSD region processor with support for 4:2:2 profile decode function

Gather buffer management for unaligned and gather load operations

Out-of-order processor that avoids deadlock in processing queues by designating a most favored instruction

Handling unaligned load operations in a multi-slice computer processor

Gather buffer management for unaligned and gather load operations

Microprocessor that fuses load and compare instructions

Handling unaligned load operations in a multi-slice computer processor

Operation of a multi-slice processor with an expanded merge fetching queue

Efficiently managing speculative finish tracking and error handling for load instructions

Dynamic translation lookaside buffer (TLB) invalidation using virtually tagged cache for load/store operations

Tracking load and store instructions and addresses in an out-of-order processor

Tracking load and store instructions and addresses in an out-of-order processor

Handling unaligned load operations in a multi-slice computer processor

Flush avoidance in a load store unit

Operation of a multi-slice processor implementing a load/store unit maintaining rejected instructions

Operation of a multi-slice processor implementing a load/store unit maintaining rejected instructions

Handling oversize store to load forwarding in a processor

Efficiently managing speculative finish tracking and error handling for load instructions

Out-of-order processor that avoids deadlock in processing queues by designating a most favored instruction

Closed-loop system for dynamically distributing memory bandwidth

Handling unaligned load operations in a multi-slice computer processor

Cache line crossing load techniques for a caching system

Cache line crossing load techniques

Fetched data in an ultra-short piped load store unit

Preventing hazard flushes in an instruction sequencing unit of a multi-slice processor

Accessing partial cachelines in a data cache

HRUSECKY DAVID A

Loading data to vector renamed register from across multiple cache lines

BUETTNER STEFAN

Reduced power consumption memory circuitry