Inventor
LIM ENG HUA
SG25 patents
⚠️ This page may combine multiple inventors who share the name “LIM ENG HUA”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
CHARTERED SEMICONDUCTOR MFG
23 patentsUS6664156B1Dec 16, 2003
Method for forming L-shaped spacers with precise width control
CHARTERED SEMICONDUCTOR MFG76 citations98
US6632712B1Oct 14, 2003
Method of fabricating variable length vertical transistors
CHARTERED SEMICONDUCTOR MFG89 citations97
US6228727B1May 8, 2001
Method to form shallow trench isolations with rounded corners and reduced trench oxide recess
CHARTERED SEMICONDUCTOR MFG142 citations97
US6350661B2Feb 26, 2002
Silicon nitride capped shallow trench isolation method for fabricating sub-micron devices with borderless contacts
CHARTERED SEMICONDUCTOR MFG49 citations95
US6265302B1Jul 24, 2001
Partially recessed shallow trench isolation method for fabricating borderless contacts
CHARTERED SEMICONDUCTOR MFG77 citations95
US6165871ADec 26, 2000
Method of making low-leakage architecture for sub-0.18 μm salicided CMOS device
CHARTERED SEMICONDUCTOR MFG55 citations95
US6762085B2Jul 13, 2004
Method of forming a high performance and low cost CMOS device
CHARTERED SEMICONDUCTOR MFG36 citations92
US6297126B1Oct 2, 2001
Silicon nitride capped shallow trench isolation method for fabricating sub-micron devices with borderless contacts
CHARTERED SEMICONDUCTOR MFG20 citations92
US6271133B1Aug 7, 2001
Optimized Co/Ti-salicide scheme for shallow junction deep sub-micron device fabrication
CHARTERED SEMICONDUCTOR MFG36 citations92
US5956137ASep 21, 1999
In-line process monitoring using micro-raman spectroscopy
CHARTERED SEMICONDUCTOR MFG31 citations92
US6468851B1Oct 22, 2002
Method of fabricating CMOS device with dual gate electrode
CHARTERED SEMICONDUCTOR MFG55 citations91
US6653227B1Nov 25, 2003
Method of cobalt silicidation using an oxide-Titanium interlayer
CHARTERED SEMICONDUCTOR MFG21 citations89
US6841441B2Jan 11, 2005
Method to produce dual gates (one metal and one poly or metal silicide) for CMOS devices using sputtered metal deposition, metallic ion implantation, or silicon implantation, and laser annealing
CHARTERED SEMICONDUCTOR MFG12 citations84
US6664153B2Dec 16, 2003
Method to fabricate a single gate with dual work-functions
CHARTERED SEMICONDUCTOR MFG18 citations84
US6610575B1Aug 26, 2003
Forming dual gate oxide thickness on vertical transistors by ion implantation
CHARTERED SEMICONDUCTOR MFG16 citations84
US6429109B1Aug 6, 2002
Method to form high k dielectric and silicide to reduce poly depletion by using a sacrificial metal between oxide and gate
CHARTERED SEMICONDUCTOR MFG18 citations84
US6605501B1Aug 12, 2003
Method of fabricating CMOS device with dual gate electrode
CHARTERED SEMICONDUCTOR MFG14 citations82
US6632745B1Oct 14, 2003
Method of forming almost L-shaped spacer for improved ILD gap fill
CHARTERED SEMICONDUCTOR MFG20 citations78
US6610604B1Aug 26, 2003
Method of forming small transistor gates by using self-aligned reverse spacer as a hard mask
CHARTERED SEMICONDUCTOR MFG10 citations73
US6383922B1May 7, 2002
Thermal stability improvement of CoSi2 film by stuffing in titanium
CHARTERED SEMICONDUCTOR MFG8 citations72
US6544848B1Apr 8, 2003
Method to form an asymmetrical non-volatile memory device using small in-situ doped polysilicon spacers
CHARTERED SEMICONDUCTOR MFG6 citations62
US6828082B2Dec 7, 2004
Method to pattern small features by using a re-flowable hard mask
CHARTERED SEMICONDUCTOR MFG1 citations52
US7615433B2Nov 10, 2009
Double anneal with improved reliability for dual contact etch stop liner scheme
CHARTERED SEMICONDUCTOR MFG1 citations50