Inventor
YEN DANIEL
SG18 patents
⚠️ This page may combine multiple inventors who share the name “YEN DANIEL”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
CHARTERED SEMICONDUCTOR MFG
16 patentsUS6632712B1Oct 14, 2003
Method of fabricating variable length vertical transistors
CHARTERED SEMICONDUCTOR MFG89 citations97
US6576526B2Jun 10, 2003
Darc layer for MIM process integration
CHARTERED SEMICONDUCTOR MFG93 citations94
US7067869B2Jun 27, 2006
Adjustable 3D capacitor
CHARTERED SEMICONDUCTOR MFG23 citations92
US6630380B1Oct 7, 2003
Method for making three-dimensional metal-insulator-metal capacitors for dynamic random access memory (DRAM) and ferroelectric random access memory (FERAM)
CHARTERED SEMICONDUCTOR MFG44 citations92
US6841441B2Jan 11, 2005
Method to produce dual gates (one metal and one poly or metal silicide) for CMOS devices using sputtered metal deposition, metallic ion implantation, or silicon implantation, and laser annealing
CHARTERED SEMICONDUCTOR MFG12 citations84
US6664153B2Dec 16, 2003
Method to fabricate a single gate with dual work-functions
CHARTERED SEMICONDUCTOR MFG18 citations84
US6610575B1Aug 26, 2003
Forming dual gate oxide thickness on vertical transistors by ion implantation
CHARTERED SEMICONDUCTOR MFG16 citations84
US6429109B1Aug 6, 2002
Method to form high k dielectric and silicide to reduce poly depletion by using a sacrificial metal between oxide and gate
CHARTERED SEMICONDUCTOR MFG18 citations84
US6605501B1Aug 12, 2003
Method of fabricating CMOS device with dual gate electrode
CHARTERED SEMICONDUCTOR MFG14 citations82
US6689643B2Feb 10, 2004
Adjustable 3D capacitor
CHARTERED SEMICONDUCTOR MFG7 citations73
US6610604B1Aug 26, 2003
Method of forming small transistor gates by using self-aligned reverse spacer as a hard mask
CHARTERED SEMICONDUCTOR MFG10 citations73
US6713335B2Mar 30, 2004
Method of self-aligning a damascene gate structure to isolation regions
CHARTERED SEMICONDUCTOR MFG11 citations66
US6544848B1Apr 8, 2003
Method to form an asymmetrical non-volatile memory device using small in-situ doped polysilicon spacers
CHARTERED SEMICONDUCTOR MFG6 citations62
US6803305B2Oct 12, 2004
Method for forming a via in a damascene process
CHARTERED SEMICONDUCTOR MFG4 citations60
US6686279B2Feb 3, 2004
Method for reducing gouging during via formation
CHARTERED SEMICONDUCTOR MFG4 citations58
US6828082B2Dec 7, 2004
Method to pattern small features by using a re-flowable hard mask
CHARTERED SEMICONDUCTOR MFG1 citations52