Inventor

AGARWALA SANJIVE

US32 patents

⚠️ This page may combine multiple inventors who share the name “AGARWALA SANJIVE”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

AGARWALA SANJIVE

TEXAS INSTRUMENTS INC

Hub interface unit and application unit interfaces for expanded direct memory access processor

Unified memory system architecture including cache and directly addressable static random access memory

Pipelined microprocessor with efficient self-modifying code detection and handling

Superscalar memory transfer controller in multilevel memory organization

Circuit and method for detecting if a sum of two multidigit numbers equals a third multidigit number prior to availability of the sum

Method of detecting arithmetic or logical computation result

Programmable built in self test of memory

Request queue manager in transfer controller with hub and ports

Configuration bus reconfigurable/reprogrammable interface for expanded direct memory access processor

Effective channel priority processing for transfer controller with hub and ports

Programmer initiated cache block operations

Method and apparatus for operating one or more caches in conjunction with direct memory access controller

Multilevel cache system coherence with memory selectively configured as cache or direct access memory and direct memory access

Unified multilevel memory system architecture which supports both cache and addressable SRAM

Automated method for testing cache

Parallel transfer size calculation and annulment determination in transfer controller with hub and ports

External direct memory access processor implementation that includes a plurality of priority levels stored in request queue

Method for timing-directed circuit optimizations

Independent source read and destination write enhanced DMA

External direct memory access processor interface to centralized transaction processor

Timing window elimination in self-modifying direct memory access processors

Circuit and method for detecting if a sum of two multibit numbers equals a third multibit constant number prior to availability of the sum

Cache read miss request invalidation prevention method

Electrical fuse control of memory slowdown

Electrical fuse control of memory slowdown

Write allocation counter for transfer controller with hub and ports

Transfer request bus node for transfer controller with hub and ports

Hardware configurable hub interface unit

Command re-ordering in hub interface unit based on priority

Active ports in a transfer controller with hub and ports

Concurrent read response acknowledge enhanced direct memory access unit

CHACHAD ABHIJEET ASHOK

Cache with multiple access pipelines