Inventor

DELP GARY SCOTT

US32 patents

⚠️ This page may combine multiple inventors who share the name “DELP GARY SCOTT”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

DELP GARY SCOTT

IBM

Method and apparatus for resource allocation with guarantees

Apparatus and method for segmentation and time synchronization of the transmission of a multiple program multimedia data stream

Dynamically-tunable memory controller

Earliest deadline first communications cell scheduler and scheduling method for transmitting earliest deadline cells first

Communications cell scheduler and scheduling method for providing proportional use of network bandwith

Method and apparatus for producing transmission control protocol checksums using internet protocol fragmentation

System and method for management a communications buffer

Method and apparatus for detecting and controlling data stream splicing in ATM networks

Configurable cache with variable, dynamically addressable line sizes

Dynamically-tunable memory controller

Apparatus and method for predicted response generation

System for selectively and cumulatively grouping packets from different sessions upon the absence of exception condition and sending the packets after preselected time conditions

Communications methods and gigabit ethernet communications adapter providing quality of service and receiver connection speed differentiation

Apparatus and method for reassembling frame data into stream data

Cell/frame scheduling method and communications cell/frame scheduler

Method and apparatus for enhanced scatter mode allowing user data to be page aligned

Independent control of DMA and I/O resources for mixed-endian computing systems

Rate based memory replacement mechanism for replacing cache entries when the cache is full

Method and apparatus for queuing and triggering data flow streams for ATM networks

Method and apparatus for implementing virtual memory having multiple selected page sizes

Integrated circuit with a VLSI chip control and monitor interface, and apparatus and method for performing operations on an integrated circuit using the same

Communications adapter for implementing communications in a network and providing multiple modes of communications

LSI CORP

Basic cell architecture for structured application-specific integrated circuits

Methods and structures for improved buffer management and dynamic adaptation of flow control status in high-speed communication networks

Methods and structures for improved buffer management and dynamic adaption of flow control status in high-speed communication networks

Suite of tools to design integrated circuits

Flexible template having embedded gate array and composable memory for integrated circuits

LSI LOGIC CORP

Placement of configurable input/output buffer structures during design of integrated circuits

Simplified process to design integrated circuits

Automated selection and placement of memory during design of an integrated circuit

Designing and testing the interconnection of addressable devices of integrated circuits

VENKATRAMAN RAMNATH

Basic cell architecture for structured application-specific integrated circuits