Inventor

CHOU YUAN C

US41 patents

⚠️ This page may combine multiple inventors who share the name “CHOU YUAN C”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

CHOU YUAN C

CHOU YUAN C

Method of read-set and write-set management by distinguishing between shared and non-shared memory regions

Reducing power consumption and resource utilization during miss lookahead

Selectively dropping prefetch requests based on prefetch accuracy information

Branch misprediction recovery mechanism for microprocessors

Handling dependency conditions between machine instructions

Correlation-based instruction prefetching

Mitigation of thread hogs on a threaded processor and prevention of allocation of resources to one or more instructions following a load miss

Non-coherent store instruction for fast inter-strand data communication for processors with write-through L1 caches

Prefetching load data in lookahead mode and invalidating architectural registers instead of writing results for retiring instructions

Apparatus and method for handling dependency conditions between floating-point instructions

Method and system for optimizing processor performance by regulating issue of pre-fetches to hot cache sets

SUN MICROSYSTEMS INC

Method and apparatus for dynamically allocating registers in a windowed architecture

Multi-stride prefetcher with a recurring prefetch table

Method and system for efficient implementation of very large store buffer

Method and apparatus for selectively executing different executable code versions which are optimized in different ways

Method and apparatus for performing register file checkpointing to support speculative execution within a processor

Value prediction for missing read operations instances

Structure and method for achieving very large lookahead instruction window via non-sequential instruction fetch and issue

Efficient on-chip instruction and data caching for chip multiprocessors

Hardware-based technique for improving the effectiveness of prefetching during scout mode

Method and structure for correlation-based prefetching

Software-based technique for improving the effectiveness of prefetching during scout mode

ORACLE INT CORP

Facilitating prefetching for data streams with multiple strides

Filtering out redundant software prefetch instructions

Prefetch bandwidth throttling by dynamically adjusting miss buffer prefetch-dropping thresholds

Processor efficiency by combining working and architectural register files

Processor efficiency by combining working and architectural register files

Register window performance via lazy register fills

Prefetching method and apparatus

APPLE INC

Processing of synchronization barrier instructions

Shared learning table for load value prediction and load address prediction

Early load execution via constant address and stride prediction

Re-use of speculative control transfer instruction results from wrong path

Re-use of speculative load instruction results from wrong path

Managing table accesses for tagged geometric length (TAGE) load value prediction

ORACLE AMERICA INC

Accuracy of correlation prefetching via block correlation and adaptive prefetch degree selection

Efficient caching of stores in scalable chip multi-threaded systems

Event address register history buffers for supporting profile-guided and dynamic optimizations

Missing store operation accelerator

DURBHAKULA SURYANARAYANA MURTHY

Adaptive stride prefetcher

GOLLA ROBERT T

Processor operating mode for mitigating dependency conditions between instructions having different operand sizes