Inventor
HOLLAWAY JR JOHN T
US12 patents
Patents
12 patentsUS9176877B2Nov 3, 2015
Provision of early data from a lower level cache memory
IBM10 citations84
US9058273B1Jun 16, 2015
Frequency determination across an interface of a data processing system
IBM9 citations83
US10223186B2Mar 5, 2019
Coherency error detection and reporting in a processor
IBM3 citations72
US11580058B1Feb 14, 2023
Hierarchical ring-based interconnection network for symmetric multiprocessors
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US9495312B2Nov 15, 2016
Determining command rate based on dropped commands
IBM2 citations62
US9495314B2Nov 15, 2016
Determining command rate based on dropped commands
IBM2 citations62
US9286220B2Mar 15, 2016
Provision of early data from a lower level cache memory
IBM2 citations62
US7984256B2Jul 19, 2011
Data processing system and method in which a participant initiating a read operation protects data integrity
IBM3 citations62
US7543116B2Jun 2, 2009
Data processing system, cache system and method for handling a flush operation in a data processing system having multiple coherency domains
IBM4 citations62
US12099463B2Sep 24, 2024
Hierarchical ring-based interconnection network for symmetric multiprocessors
IBM0 citations61
US9122608B2Sep 1, 2015
Frequency determination across an interface of a data processing system
IBM0 citations51
US7571357B2Aug 4, 2009
Memory wrap test mode using functional read/write buffers
IBM1 citations51