Inventor

YU TSUNG-HSING

TW45 patents

⚠️ This page may combine multiple inventors who share the name “YU TSUNG-HSING”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

YU TSUNG-HSING

TAIWAN SEMICONDUCTOR MFG CO LTD

Dislocation stress memorization technique (DSMT) on epitaxial channel devices

Process design to improve transistor variations and performance

Multi-gate semiconductor devices and methods of forming the same

Semiconductor device and manufacturing method thereof

Epitaxial channel with a counter-halo implant to improve analog gain

Dislocation stress memorization technique (DSMT) on epitaxial channel devices

Semiconductor device having gate dielectric surrounding at least some of channel region and gate electrode surrounding at least some of gate dielectric

Method for manufacturing semiconductor structure

Structure and method for integrated circuit

Semiconductor structures and methods for multi-dimension of nanowire diameter to improve drive current

Semiconductor structure and manufacturing method thereof

Structure and method for integrated circuit

Variable channel strain of nanowire transistors to improve drive current

Semiconductor device having multiple active area layers and its formation thereof

Semiconductor structures and methods for multi-level band gap energy of nanowire transistors to improve drive current

Semiconductor structures and methods for multi-level work function and multi-valued channel doping of nanowire transistors to improve drive current

Recess and epitaxial layer to improve transistor performance

Transistor having replacement gate and epitaxially grown replacement channel region

Transistor design

Semiconductor device with silicide-embedded stressor source and drain structure

Structure and method for integrated circuit

Semiconductor device and manufacturing method thereof

Structure and method for integrated circuit

Semiconductor device and manufacturing method thereof

Dislocation stress memorization technique (DSMT) on epitaxial channel devices

Asymmetric semiconductor device

Method of forming semiconductor device having gate dielectric surrounding at least some of channel region and gate electrode surrounding at least some of gate dielectric

Semiconductor structure and manufacturing method thereof

Process design to improve transistor variations and performance

Transistor design

Method of manufacturing an integrated circuit

Multi-gate semiconductor devices

Epitaxial channel with a counter-halo implant to improve analog gain

Semiconductor device and manufacturing method thereof

MOSFET structure with T-shaped epitaxial silicon channel

Epitaxial channel

Semiconductor transistor device with dopant profile

Counter pocket implant to improve analog gain

TAIWAN SEMICONDUCTOR MFG

Variable channel strain of nanowire transistors to improve drive current

Metal gate structure and manufacturing method thereof

WU ZHIQIANG

Integrated circuits and manufacturing methods thereof

WANG CHIH-CHING

Multi-gate semiconductor devices and methods of forming the same

HO JON-HSU

Multi-gate semiconductor devices

DHANYAKUMAR MAHAVEER SATHAIYA

MOSFET structure with T-shaped epitaxial silicon channel

LIU CHIA-WEN

Method for forming a semiconductor transistor device with optimized dopant profile