Inventor

SHEU YI-MING

TW52 patents

⚠️ This page may combine multiple inventors who share the name “SHEU YI-MING”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

SHEU YI-MING

TAIWAN SEMICONDUCTOR MFG CO LTD

Horizontal gate-all-around device having wrapped-around source and drain

Horizontal gate-all-around device having wrapped-around source and drain

Dislocation stress memorization technique (DSMT) on epitaxial channel devices

Multi-gate semiconductor devices and methods of forming the same

Semiconductor device and manufacturing method thereof

Channel strain inducing architecture and doping technique at replacement poly gate (RPG) stage

Multi-gate device

Horizontal gate all-around device having wrapped-around source and drain

Multi-gate device and method of fabrication thereof

Dislocation stress memorization technique (DSMT) on epitaxial channel devices

Epitaxial channel with a counter-halo implant to improve analog gain

Method for manufacturing semiconductor structure

Structure and method for integrated circuit

Semiconductor structure and manufacturing method thereof

Structure and method for integrated circuit

Channel strain inducing architecture and doping technique at replacement poly gate (RPG) stage

Horizontal gate all-around device having wrapped-around source and drain

Semiconductor device with silicide-embedded stressor source and drain structure

Method of fabricating a multi-gate device

Structure and method for integrated circuit

Semiconductor device and manufacturing method thereof

Structure and method for integrated circuit

Multi-gate device

Semiconductor device and manufacturing method thereof

Structure and formation method of semiconductor device structure

Dislocation stress memorization technique (DSMT) on epitaxial channel devices

Semiconductor structure and manufacturing method thereof

Multi-gate semiconductor devices

Method of manufacturing an integrated circuit

Epitaxial channel with a counter-halo implant to improve analog gain

Semiconductor device and manufacturing method thereof

Channel strain inducing architecture and doping technique at replacement poly gate (RPG) stage

TAIWAN SEMICONDUCTOR MFG

Semiconductor device having high drive current and method of manufacture therefor

Damascene gate electrode method for fabricating field effect transistor (FET) device with ion implanted lightly doped extension regions

Planarizing method for fabricating gate electrodes

Narrow width effect improvement with photoresist plug process and STI corner ion implantation

Recessed channel field effect transistor (FET) device

N/PMOS saturation current, HCE, and Vt stability by contact etch stop film modifications

Recessed gate structure with reduced current leakage and overlap capacitance

Method for fabricating a recessed channel field effect transistor (FET) device

Narrow width effect improvement with photoresist plug process and STI corner ion implantation

Method of forming a self-aligned twin well structure with a single mask

Method for reducing layout-dependent variations in semiconductor devices

Metal gate structure and manufacturing method thereof

Electrostatic discharge device protection structure

BHUWALKA KRISHNA KUMAR

Tunnel field-effect transistor with metal source

WU ZHIQIANG

Integrated circuits and manufacturing methods thereof

DIAZ CARLOS H

Method for mechanical stress enhancement in semiconductor devices

WANG CHIH-CHING

Multi-gate semiconductor devices and methods of forming the same

HO JON-HSU

Multi-gate semiconductor devices