Inventor

AVUDAIYAPPAN KARTHIKEYAN

US47 patents

⚠️ This page may combine multiple inventors who share the name “AVUDAIYAPPAN KARTHIKEYAN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

AVUDAIYAPPAN KARTHIKEYAN

INTEL CORP

Methods and systems for managing synonyms in virtually indexed physically tagged caches

Systems and methods for accessing a unified translation lookaside buffer

Methods, systems and apparatus for predicting the way of a set associative cache

Systems and methods for faster read after write forwarding using a virtual address

Systems and methods for invasive debug of a processor without processor execution of instructions

Systems and methods for acquiring data for loads at different access times from hierarchical sources using a load queue as a temporary storage buffer and completing the load early

Method and apparatus for supporting a plurality of load accesses of a cache in a single cycle to maintain throughput

Methods and systems for managing synonyms in virtually indexed physically tagged caches

Systems and methods for load canceling in a processor that is connected to an external interconnect fabric

Systems and methods for faster read after write forwarding using a virtual address

Systems and methods for non-blocking implementation of cache flush instructions

Systems and methods for maintaining the coherency of a store coalescing cache and a load cache

Systems and methods for implementing weak stream software data and instruction prefetching using a hardware data prefetcher

Systems and methods for flushing a cache with modified data

Systems and methods for load cancelling in a processor that is connected to an external interconnect fabric

Methods, systems and apparatus for predicting the way of a set associative cache

Methods, systems and apparatus for predicting the way of a set associative cache

Systems and methods for flushing a cache with modified data

Systems and methods for non-blocking implementation of cache flush instructions

Systems and methods for accessing a unified translation lookaside buffer

Systems and methods for supporting a plurality of load and store accesses of a cache

Systems and methods for maintaining the coherency of a store coalescing cache and a load cache

Systems and methods for non-blocking implementation of cache flush instructions

Systems and methods for read request bypassing a last level cache that interfaces with an external fabric

Systems and methods for acquiring data for loads at different access times from hierarchical sources using a load queue as a temporary storage buffer and completing the load early

Systems and methods for invasive debug of a processor without processor execution of instructions

Method and apparatus for supporting a plurality of load accesses of a cache in a single cycle to maintain throughput

Systems and methods for managing inter-CPU interrupts between multiple CPUs

Systems and methods for managing inter-CPU interrupts between multiple CPUs

Systems and methods for invalidating directory of non-home locations ways

Methods and systems for tracking addresses stored in non-home cache locations

Method and apparatus for providing hardware support for self-modifying code

AVUDAIYAPPAN KARTHIKEYAN

Systems and methods for accessing a unified translation lookaside buffer

Memory utilization tracking

Cache replacement policy

Systems and methods for load canceling in a processor that is connected to an external interconnect fabric

Systems and methods for supporting a plurality of load and store accesses of a cache

Systems and methods for maintaining the coherency of a store coalescing cache and a load cache

Systems and methods for flushing a cache with modified data

Systems and methods for supporting a plurality of load accesses of a cache in a single cycle

SOFT MACHINES INC

Systems and methods for faster read after write forwarding using a virtual address

Systems and methods for accessing a unified translation lookaside buffer

Systems and methods for implementing weak stream software data and instruction prefetching using a hardware data prefetcher

MICROSOFT TECHNOLOGY LICENSING LLC

Fetching non-zero data

Accelerating processing based on sparsity for neural network hardware processors

SUN MICROSYSTEMS INC

Ring counter based starvation free weighted priority encoded arbiter

MICROSOFT TECH LICENSING LLC

Multipurpose multiply-accumulator array