Inventor
RAMANI SRINIVASAN
US47 patents
⚠️ This page may combine multiple inventors who share the name “RAMANI SRINIVASAN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
IBM
31 patentsUS7453798B2Nov 18, 2008
Active flow management with hysteresis
IBM16 citations83
US10382267B2Aug 13, 2019
Managing servers with quality of service assurances
IBM2 citations73
US9952651B2Apr 24, 2018
Deterministic current based frequency optimization of processor chip
IBM2 citations73
US9948513B2Apr 17, 2018
Managing servers with quality of service assurances
IBM2 citations73
US9778726B2Oct 3, 2017
Deterministic current based frequency optimization of processor chip
IBM2 citations73
US9354943B2May 31, 2016
Power management for multi-core processing systems
IBM4 citations73
US10901710B2Jan 26, 2021
Processor that includes a special store instruction used in regions of a computer program where memory aliasing may occur
IBM1 citations71
US10331162B2Jun 25, 2019
Power series truncation using constant tables for function interpolation in transcendental functions
IBM2 citations71
US10002212B2Jun 19, 2018
Virtual power management multiprocessor system simulation
IBM2 citations71
US9563724B2Feb 7, 2017
Virtual power management multiprocessor system simulation
IBM2 citations71
US7249331B2Jul 24, 2007
Architectural level throughput based power modeling methodology and apparatus for pervasively clock-gated processor cores
IBM8 citations71
US9626229B1Apr 18, 2017
Processor performance monitoring unit synchronization
IBM4 citations69
US10680892B2Jun 9, 2020
Managing servers with quality of service assurances
IBM0 citations52
US9471398B2Oct 18, 2016
Global lock contention predictor
IBM1 citations52
US9471397B2Oct 18, 2016
Global lock contention predictor
IBM1 citations52
US9323574B2Apr 26, 2016
Processor power optimization with response time assurance
IBM0 citations52
US10678523B2Jun 9, 2020
Processor that detects memory aliasing in hardware and assures correct operation when memory aliasing occurs
IBM0 citations51
US10664250B2May 26, 2020
Performing register promotion optimizations in a computer program in regions where memory aliasing may occur and executing the computer program on processor hardware that detects memory aliasing
IBM0 citations51
US10509635B2Dec 17, 2019
Processor that includes a special store instruction used in regions of a computer program where memory aliasing may occur
IBM0 citations51
US10228921B2Mar 12, 2019
Compiler that performs register promotion optimizations in regions of code where memory aliasing may occur
IBM0 citations51
US10228918B2Mar 12, 2019
Processor that detects memory aliasing in hardware and assures correct operation when memory aliasing occurs
IBM0 citations51
US10169010B2Jan 1, 2019
Performing register promotion optimizations in a computer program in regions where memory aliasing may occur and executing the computer program on processor hardware that detects memory aliasing
IBM0 citations51
US10169009B2Jan 1, 2019
Processor that detects memory aliasing in hardware and assures correct operation when memory aliasing occurs
IBM0 citations51
US9934009B2Apr 3, 2018
Processor that includes a special store instruction used in regions of a computer program where memory aliasing may occur
IBM0 citations51
US9515663B2Dec 6, 2016
Dynamic prescaling for performance counters
IBM0 citations51
US9419625B2Aug 16, 2016
Dynamic prescaling for performance counters
IBM1 citations51
US10671110B2Jun 2, 2020
Power series truncation using constant tables for function interpolation in transcendental functions
IBM0 citations50
US9568986B2Feb 14, 2017
System-wide power conservation using memory cache
IBM1 citations50
US7818696B2Oct 19, 2010
Architectural level throughput based power modeling methodology and apparatus for pervasively clock-gated processor cores
IBM1 citations50
US9541985B2Jan 10, 2017
Energy efficient optimization in multicore processors under quality of service (QoS)/performance constraints
IBM0 citations48
US9535486B2Jan 3, 2017
Energy efficient optimization in multicore processors under quality of service (QoS)/performance constraints
IBM0 citations48
RAMANI SRINIVASAN
4 patentsUS8578168B2Nov 5, 2013
Method and apparatus for preparing and verifying documents
RAMANI SRINIVASAN8 citations79
US8780402B2Jul 15, 2014
Document and method of producing a document
RAMANI SRINIVASAN0 citations47
US8442991B2May 14, 2013
Information access device and network
RAMANI SRINIVASAN0 citations47
US10102439B2Oct 16, 2018
Document verification method and system
RAMANI SRINIVASAN0 citations34
ADAR ETAI
3 patentsUS8589922B2Nov 19, 2013
Performance monitor design for counting events generated by thread groups
ADAR ETAI7 citations82
US8489787B2Jul 16, 2013
Sharing sampled instruction address registers for efficient instruction sampling in massively multithreaded processors
ADAR ETAI14 citations82
US8601193B2Dec 3, 2013
Performance monitor design for instruction profiling using shared counters
ADAR ETAI2 citations61