Inventor
CHU SAM GAT-SHANG
US28 patents
Patents
28 patentsUS6901546B2May 31, 2005
Enhanced debug scheme for LBIST
IBM56 citations94
US6826090B1Nov 30, 2004
Apparatus and method for a radiation resistant latch
IBM21 citations92
US6046606AApr 4, 2000
Soft error protected dynamic circuit
IBM40 citations92
US5852373ADec 22, 1998
Static-dynamic logic circuit
IBM38 citations92
US6052008AApr 18, 2000
Generation of true and complement signals in dynamic circuits
IBM21 citations88
US7668035B2Feb 23, 2010
Memory circuits with reduced leakage power and design structures for same
IBM14 citations84
US7202704B2Apr 10, 2007
Leakage sensing and keeper circuit for proper operation of a dynamic circuit
IBM14 citations84
US6825691B1Nov 30, 2004
Apparatus and method for a radiation resistant latch with integrated scan
IBM19 citations84
US6002271ADec 14, 1999
Dynamic MOS logic circuit without charge sharing noise
IBM19 citations83
US6922818B2Jul 26, 2005
Method of power consumption reduction in clocked circuits
IBM14 citations82
US7562273B2Jul 14, 2009
Register file cell with soft error detection and circuits and methods using the cell
IBM7 citations74
US6934181B2Aug 23, 2005
Reducing sub-threshold leakage in a memory array
IBM9 citations74
US6914450B2Jul 5, 2005
Register-file bit-read method and apparatus
IBM8 citations74
US7243209B2Jul 10, 2007
Apparatus and method for speeding up access time of a large register file with wrap capability
IBM8 citations72
US7679973B2Mar 16, 2010
Register file
IBM5 citations71
US7443737B2Oct 28, 2008
Register file
IBM5 citations71
US6914849B2Jul 5, 2005
Method and apparatus for reducing power consumption in a memory array with dynamic word line driver/decoders
IBM8 citations69
US7506230B2Mar 17, 2009
Transient noise detection scheme and apparatus
IBM6 citations63
US7302553B2Nov 27, 2007
Apparatus, system and method for quickly determining an oldest instruction in a non-moving instruction queue
IBM3 citations63
US7012839B1Mar 14, 2006
Register file apparatus and method incorporating read-after-write blocking using detection cells
IBM4 citations63
US7002860B2Feb 21, 2006
Multilevel register-file bit-read method and apparatus
IBM4 citations63
US7474574B1Jan 6, 2009
Shift register latch with embedded dynamic random access memory scan only cell
IBM5 citations62
US7663963B2Feb 16, 2010
Apparatus and method for providing multiple reads/writes using a 2Read/2Write register file array
IBM2 citations61
US11119774B2Sep 14, 2021
Slice-target register file for microprocessor
IBM0 citations52
US7551475B2Jun 23, 2009
Data shifting through scan registers
IBM1 citations52
US7142463B2Nov 28, 2006
Register file method incorporating read-after-write blocking using detection cells
IBM0 citations52
US7400548B2Jul 15, 2008
Method for providing multiple reads/writes using a 2read/2write register file array
IBM1 citations51
US7015723B2Mar 21, 2006
Dynamic-static logical control element for signaling an interval between the end of a control signal and a logical evaluation
IBM0 citations42