Inventor

ASAAD SAMEH W

US42 patents

⚠️ This page may combine multiple inventors who share the name “ASAAD SAMEH W”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

ASAAD SAMEH W

IBM

System and method for adaptive run-time reconfiguration for a reconfigurable instruction set co-processor architecture

All-in-one mobile docking station and system used therewith

System and intelligent dock using a symmetric extended bus bridge and method therefor

Hardware implementation of a tournament tree sort algorithm

Tunable hardware sort engine for performing composite sorting algorithms

Generating clock signals for a cycle accurate, cycle reproducible FPGA based hardware accelerator

Generating clock signals for a cycle accurate, cycle reproducible FPGA based hardware accelerator

Scalable acceleration of database query operations

Accelerating multiple query processing operations

Hardware implementation of a tournament tree sort algorithm

Tunable hardware sort engine for performing composite sorting algorithms

Communications system including symmetric bus bridge and method used therewith

Data filtering using a plurality of hardware accelerators

Tunable hardware sort engine for performing composite sorting algorithms

Tunable hardware sort engine for performing composite sorting algorithms

Scalable acceleration of database query operations

Scalable acceleration of database query operations

Hardware projection of fixed and variable length columns of database tables

Radix sort with read-only key

System and method for instruction memory storage and processing based on backwards branch control information

Cycle accurate and cycle reproducible memory for an FPGA based hardware accelerator

Method and system for high resolution display connect through extended bridge

Data filtering using a plurality of hardware accelerators

Cycle accurate and cycle reproducible memory for an FPGA based hardware accelerator

Accelerating multiple query processing operations

Offloading projection of fixed and variable length database columns

Extendible input/output data mechanism for accelerators

Extendible input/output data mechanism for accelerators

Offloading projection of fixed and variable length database columns

Offloading projection of fixed and variable length database columns

Radix sort with read-only key

System and method for adaptive run-time reconfiguration for a reconfigurable instruction set co-processor architecture

Enhanced conversion between geohash codes and corresponding longitude/latitude coordinates

Offloading projection of fixed and variable length database columns

Data filtering using a plurality of hardware accelerators

Spatial predicates evaluation on geohash-encoded geographical regions

Spatial predicates evaluation on geohash-encoded geographical regions

ASAAD SAMEH W

Generating data feed specific parser circuits

System and method for adaptive run-time reconfiguration for a reconfigurable instruction set co-processor architecture

Cycle accurate and cycle reproducible memory for an FPGA based hardware accelerator

Method and infrastructure for cycle-reproducible simulation on large scale digital circuits on a coordinated set of field-programmable gate arrays (FPGAs)

SUKHWANI BHARAT

Hardware-accelerated relational joins