Inventor
JASER IHAB
US11 patents
⚠️ This page may combine multiple inventors who share the name “JASER IHAB”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
MICROSEMI STORAGE SOLUTIONS (US) INC
4 patentsUS9590656B2Mar 7, 2017
System and method for higher quality log likelihood ratios in LDPC decoding
MICROSEMI STORAGE SOLUTIONS (US) INC26 citations93
US9454414B2Sep 27, 2016
System and method for accumulating soft information in LDPC decoding
MICROSEMI STORAGE SOLUTIONS (US) INC25 citations93
US9448881B1Sep 20, 2016
Memory controller and integrated circuit device for correcting errors in data read from memory cells
MICROSEMI STORAGE SOLUTIONS (US) INC16 citations92
US9477562B1Oct 25, 2016
Apparatus and method for minimizing exclusive-OR (XOR) computation time
MICROSEMI STORAGE SOLUTIONS (US) INC0 citations41
MICROCHIP TECH INC
3 patentsUS12197320B2Jan 14, 2025
System and method for enhancing flash channel utilization
MICROCHIP TECH INC0 citations53
US12468473B2Nov 11, 2025
System and method for centralized management of workload and parallel service of prioritized requests
MICROCHIP TECH INC0 citations45
US11914899B2Feb 27, 2024
System for managing access to a memory resource by multiple users
MICROCHIP TECH INC0 citations44
ONUFRYK PETER Z
2 patentsUS8554968B1Oct 8, 2013
Interrupt technique for a nonvolatile memory controller
ONUFRYK PETER Z66 citations97
US8588228B1Nov 19, 2013
Nonvolatile memory controller with host controller interface for retrieving and dispatching nonvolatile memory commands in a distributed manner
ONUFRYK PETER Z32 citations90
PMC SIERRA US INC
2 patentsUS9128858B1Sep 8, 2015
Apparatus and method for adjusting a correctable raw bit error rate limit in a memory system using strong log-likelihood (LLR) values
PMC SIERRA US INC47 citations94
US9092353B1Jul 28, 2015
Apparatus and method based on LDPC codes for adjusting a correctable raw bit error rate limit in a memory system
PMC SIERRA US INC33 citations94