Inventor

PRAKASH ABHIJITH

US47 patents

⚠️ This page may combine multiple inventors who share the name “PRAKASH ABHIJITH”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

PRAKASH ABHIJITH

SANDISK TECHNOLOGIES LLC

Countermeasures for first read issue

Read operation or word line voltage refresh operation in memory device with reduced peak current

Reducing post-read disturb in a nonvolatile memory device

Refresh operations for dedicated groups of blocks of memory cells

Erase method for non-volatile memory with multiple tiers

Memory programming with selectively skipped bitscans and fewer verify pulses for performance improvement

Multi-level program pulse for programming single level memory cells to reduce damage

Temperature and cycling dependent refresh operation for memory cells

Multi-stage programming techniques with three states per memory cell parity

Control gate signal for data retention in nonvolatile memory

Recovery pulses to counter cumulative read disturb

Temperature-dependent word line voltage and discharge rate for refresh read of non-volatile memory

Two-side staircase pre-charge in sub-block mode of three-tier non-volatile memory architecture

Techniques for erasing the memory cells of edge word lines

Control gate signal for data retention in nonvolatile memory

Systems and methods for compensating for erase speed variations due to semi-circle SGD

Programming techniques with fewer verify pulses to improve performance

Refresh operations for memory cells based on susceptibility to read errors

Three dimensional memory device containing truncated channels and method of operating the same with different erase voltages for different bit lines

Edge word line data retention improvement for memory apparatus with on-pitch semi-circle drain side select gate technology

Method to fix cumulative read induced drain side select gate downshift in memory apparatus with on-pitch drain side select gate

Bit line modulation to compensate for cell source variation

Pre-position dummy word line to facilitate write erase capability of memory apparatus

Refresh frequency-dependent system-level trimming of verify level offsets for non-volatile memory

Memory device that is optimized for operation at different temperatures

Application based verify level offsets for non-volatile memory

Countermeasures for periodic over programming for non-volatile memory

SANDISK TECHNOLOGIES INC

Dynamic sensing scheme to compensate for threshold voltage shift during sensing in a memory device

Plane and block location dependent voltage biases in NAND memory

Real time ramp rate adjustment for better performance and current consumption tradeoff

Variable foggy verify levels for selected checkpoint states for non-volatile memory apparatuses

Word line zone based unselect word line bias to enable single-side gate-induced drain leakage erase

Regular transistor threshold voltage refresh for semi-circle drain side select gates

Positive sensing in low power operation mode in a memory device

Energy efficient fast read in a memory device

Loop dependent bit line and read biases in a memory device

Generation of quick pass write biases in a memory device

Delayed select gate ramp-up for peak read current consumption reduction for non-volatile memory apparatus

Evolving bad block detection in non-volatile memory

Memory die management

WESTERN DIGITAL TECH INC

Reducing post-read disturb in a nonvolatile memory device

Intermediate re-verify for achieving tighter threshold voltage distributions in a memory device

Methods to improve current consumption and read time in successive reads

Data retention-specific refresh read

Reducing time-tag read errors with respect to non-volatile memory structures

Non-volatile memory with multiple data resolutions

Single block mode block handling for single-side GIDL erase