Inventor

NAFFZIGER SAMUEL

US35 patents

⚠️ This page may combine multiple inventors who share the name “NAFFZIGER SAMUEL”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

NAFFZIGER SAMUEL

ADVANCED MICRO DEVICES INC

Flexibile interfaces using through-silicon via technology

Swizzling in 3D stacked memory

Arrangement and thermal management of 3D stacked dies

GPU chiplets using high bandwidth crosslinks

Arrangement and thermal management of 3D stacked dies

Arrangement and thermal management of 3D stacked dies

Refreshing displays using on-die cache

Adaptive resizable cache/LCM for improved power

Performance management during power supply voltage droop

Self-adjusting clock doubler and integrated circuit clock distribution system using same

Adaptive temperature and power calculation for integrated circuits

Configurable multiple-die graphics processing unit

Performance state boost for multi-core integrated circuit

Power efficiency optimization in throughput-based workloads

Adaptive voltage scaling based on stage transitions or ring oscillator revolutions

Mission mode Vmin prediction and calibration

HEWLETT PACKARD DEVELOPMENT CO

Adapting VLSI clocking to short term voltage transients

Method and apparatus for conserving power on a multiprocessor integrated circuit

Voltage modulation for increased reliability in an integrated circuit

System, method and apparatus for conserving power consumed by a system having a processor integrated circuit

Method and apparatus for multi-core processor integrated circuit having functional elements configurable as core elements and as system device elements

Count calibration for synchronous data transfer between clock domains

Apparatus for cache compression engine for data compression of on-chip caches to increase effective cache size

Method and apparatus for improving yield by decommissioning optional units on a CPU due to manufacturing defects

System and method for synchronizing multiple variable-frequency clock generators

Central processing unit with multiple clock zones and operating method

Method and system for detecting dropped micro-packets

Adaptable data path for synchronous data transfer between clock domains

Edge calibration for synchronous data transfer between clock domains

NAFFZIGER SAMUEL

System and method for implementing an integrated circuit having dynamically variable power limit

System and method for implementing an integrated circuit having a dynamically variable power limit

WUU JOHN

Arrangement and thermal management of 3D stacked dies

PALISETTI VASANT

Identification of critical enables using MEA and WAA metrics

ONESTA IP LLC

GPU chiplets using high bandwidth crosslinks

GOLD SPENCER

10T SRAM for graphics processing