Inventor
LEE MICHAEL JU HYEOK
US31 patents
Patents
31 patentsUS6433589B1Aug 13, 2002
Sense amplifier and method for sensing signals in a silicon-on-insulator integrated circuit
IBM84 citations98
US6826090B1Nov 30, 2004
Apparatus and method for a radiation resistant latch
IBM21 citations92
US6046606AApr 4, 2000
Soft error protected dynamic circuit
IBM40 citations92
US5852373ADec 22, 1998
Static-dynamic logic circuit
IBM38 citations92
US6052008AApr 18, 2000
Generation of true and complement signals in dynamic circuits
IBM21 citations88
US7202704B2Apr 10, 2007
Leakage sensing and keeper circuit for proper operation of a dynamic circuit
IBM14 citations84
US6825691B1Nov 30, 2004
Apparatus and method for a radiation resistant latch with integrated scan
IBM19 citations84
US6107852AAug 22, 2000
Method and device for the reduction of latch insertion delay
IBM16 citations83
US6002271ADec 14, 1999
Dynamic MOS logic circuit without charge sharing noise
IBM19 citations83
US7283404B2Oct 16, 2007
Content addressable memory including a dual mode cycle boundary latch
IBM11 citations80
US6934181B2Aug 23, 2005
Reducing sub-threshold leakage in a memory array
IBM9 citations74
US6914450B2Jul 5, 2005
Register-file bit-read method and apparatus
IBM8 citations74
US7116569B2Oct 3, 2006
Method and apparatus for selecting operating characteristics of a content addressable memory by using a compare mask
IBM7 citations71
US7092270B2Aug 15, 2006
Apparatus and method for detecting multiple hits in CAM arrays
IBM8 citations71
US6960941B2Nov 1, 2005
Latch circuit capable of ensuring race-free staging for signals in dynamic logic circuits
IBM8 citations71
US7167385B2Jan 23, 2007
Method and apparatus for controlling the timing of precharge in a content addressable memory system
IBM9 citations70
US7936198B2May 3, 2011
Progamable control clock circuit for arrays
IBM4 citations63
US7506230B2Mar 17, 2009
Transient noise detection scheme and apparatus
IBM6 citations63
US7012839B1Mar 14, 2006
Register file apparatus and method incorporating read-after-write blocking using detection cells
IBM4 citations63
US7002860B2Feb 21, 2006
Multilevel register-file bit-read method and apparatus
IBM4 citations63
US7552413B2Jun 23, 2009
System and computer program for verifying performance of an array by simulating operation of edge cells in a full array model
IBM3 citations62
US6341095B1Jan 22, 2002
Apparatus for increasing pulldown rate of a bitline in a memory device during a read operation
IBM6 citations62
US7813189B2Oct 12, 2010
Array data input latch and data clocking scheme
IBM3 citations61
US9042149B2May 26, 2015
Volatile memory access via shared bitlines
IBM1 citations52
US7142463B2Nov 28, 2006
Register file method incorporating read-after-write blocking using detection cells
IBM0 citations52
US7424691B2Sep 9, 2008
Method for verifying performance of an array by simulating operation of edge cells in a full array model
IBM1 citations51
US6037804AMar 14, 2000
Reduced power dynamic logic circuit that inhibits reevaluation of stable inputs
IBM0 citations51
US7099201B1Aug 29, 2006
Multifunctional latch circuit for use with both SRAM array and self test device
IBM1 citations49
US7015723B2Mar 21, 2006
Dynamic-static logical control element for signaling an interval between the end of a control signal and a logical evaluation
IBM0 citations42
US7804728B2Sep 28, 2010
Information handling system with SRAM precharge power conservation
IBM0 citations41
US7466647B2Dec 16, 2008
Efficient muxing scheme to allow for bypass and array access
IBM0 citations36