Inventor

NGUYEN BAI

US33 patents

⚠️ This page may combine multiple inventors who share the name “NGUYEN BAI”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

NGUYEN BAI

LATTICE SEMICONDUCTOR CORP

Methods for configuring FPGA&#39;s having variable grain components for providing time-shared access to interconnect resources

Scalable serializer-deserializer architecture and programmable interface

FPGA integrated circuit having embedded sram memory blocks each with statically and dynamically controllable read mode

Programmable input/output block (IOB) in FPGA integrated circuits

Programmable logic device with power-saving architecture

Programmable logic device with a double data rate SDRAM interface

Field programmable gate array having embedded memory with configurable depth and width

Methods for configuring FPGA&#39;s having variable grain blocks and shared logic for providing symmetric routing of result output to differently-directed and tristateable interconnect resources

I/O buffer architecture for programmable devices

FPGA integrated circuit having embedded sram memory blocks with registered address and data input sections

Programmable logic device with power-saving architecture

Programmable logic device with a multi-data rate SDRAM interface

Programmable logic devices with distributed memory and non-volatile memory

Programmable logic devices with distributed memory

Input/output systems and methods

VANTIS CORP

Efficient interconnect network for use in FPGA device having variable grain architecture

Synthesis-friendly FPGA architecture with variable length and variable timing interconnect

FPGA integrated circuit having embedded SRAM memory blocks and interconnect channel for broadcasting address and control signals

Methods for configuring FPGA&#39;s having variable grain components for providing time-shared access to interconnect resources

FPGA device and method that includes a variable grain function architecture for implementing configuration logic blocks and a complimentary variable length interconnect architecture for providing configurable routing between configuration logic blocks

Tileable and compact layout for super variable grain blocks within FPGA device

Dual port SRAM memory for run time use in FPGA integrated circuits

Semiconductor-oxide-semiconductor capacitor formed in integrated circuit

FPGA integrated circuit having embedded SRAM memory blocks with registered address and data input sections

Methods for configuring FPGA&#39;s having variable grain blocks and logic for providing time-shared access to interconnect resources

Multi-port SRAM cell array having plural write paths including for writing through addressable port and through serial boundary scan

Methods for configuring FPGA&#39;s having variable grain blocks and shared logic for providing symmetric routing of result output to differently-directed and tristateable interconnect resources

Methods for configuring FPGA&#39;s having variable grain components for providing time-shared access to interconnect resources

EMPOWER SEMICONDUCTOR INC

High voltage stage for switching regulator

Dual-output switched-capacitor power converter

Dual-output switched-capacitor power converter

High voltage stage for switching regulator

High voltage switching regulator with n-channel high-side switches

Methods for configuring FPGA's having variable grain components for providing time-shared access to interconnect resources

Methods for configuring FPGA's having variable grain blocks and shared logic for providing symmetric routing of result output to differently-directed and tristateable interconnect resources

Methods for configuring FPGA's having variable grain components for providing time-shared access to interconnect resources

Methods for configuring FPGA's having variable grain blocks and logic for providing time-shared access to interconnect resources

Methods for configuring FPGA's having variable grain blocks and shared logic for providing symmetric routing of result output to differently-directed and tristateable interconnect resources

Methods for configuring FPGA's having variable grain components for providing time-shared access to interconnect resources