Inventor

HEIN JERRELL P

US40 patents

⚠️ This page may combine multiple inventors who share the name “HEIN JERRELL P”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

HEIN JERRELL P

SILICON LAB INC

Dual loop architecture useful for a programmable clock source and clock multiplier applications

Method and apparatus for monitoring subscriber loop interface circuitry power dissipation

Method and apparatus for temperature compensation

Multi-frequency clock synthesizer

Subscriber line interface circuitry

Separation of ring detection functions across isolation barrier for minimum power

Framed delta sigma data with unlikely delta sigma data patterns

Telephone line interface architecture using ringer inputs for caller ID data

Capacitively coupled ring detector with power provided across isolation barrier

Voltage controlled clock synthesizer

Multiple signal format output buffer

Integrated modem and line-isolation circuitry and associated method powering caller ID circuitry with power provided across an isolation barrier

Integrated circuit incorporating circuitry for determining which of at least two possible frequencies is present on an externally provided reference signal and method therefor

Digital isolation system with low power mode

Dual loop architecture useful for a programmable clock source and clock multiplier applications

Clock and data recovery circuit without jitter peaking

Architecture for minimum loop current during ringing and caller ID

Method and apparatus for freezing a communication link during a disruptive event

Architecture for minimum loop current during ringing and caller ID

Slice voltage compensation

Subscriber line interface circuitry

Subscriber line interface circuitry

Separation of ring detection functions across isolation barrier for minimum power

Subscriber loop interface circuitry having bifurcated common mode control

Low voltage sensing and control of battery referenced transistors in subscriber loop applications

Low voltage sensing and control of battery referenced transistors in subscriber loop applications

Subscriber line interface circuitry with common base audio isolation stage

Frequency margin testing

Subscriber line interface circuitry

CIRRUS LOGIC INC

Method to improve the jitter of high frequency phase locked loops used in read channels

Read/write channel write precompensation system and method using one or more delay clocks

System and method for control of low frequency input levels to an amplifier and compensation of input offsets of the amplifier

Method and system to improve single synthesizer setting times for small frequency steps in read channel circuits

Method and circuit for calibration of flash analog to digital converters

Read channel auxiliary high precision data conversion

CRYSTAL SEMICONDUCTOR CORP

Clock multiplier/jitter attenuator

Clock multiplier/jitter attenuator

SEETHAMRAJU SRISAI R

Digital hold in a phase-locked loop

AT & T BELL LAB

Temperature insensitive CMOS precision current source

AMERICAN TELEPHONE & TELEGRAPH

Analog comparator