Inventor
POUARZ TRAVIS W
US3 patents
Patents
3 patentsUS8042078B2Oct 18, 2011
Enhancing formal design verification by reusing previous results
IBM13 citations82
US7546561B2Jun 9, 2009
System and method of state point correspondence with constrained function determination
IBM5 citations60
US7979732B2Jul 12, 2011
Efficient utilization of a multi-source network of control logic to achieve timing closure in a clocked logic circuit
IBM5 citations54