Inventor
JAIN DINESH K
US37 patents
⚠️ This page may combine multiple inventors who share the name “JAIN DINESH K”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
VIA ALLIANCE SEMICONDUCTOR CO LTD
23 patentsUS9715456B2Jul 25, 2017
Apparatus and method for storage and decompression of configuration data
VIA ALLIANCE SEMICONDUCTOR CO LTD2 citations84
US9535847B2Jan 3, 2017
Apparatus and method for compression of configuration data
VIA ALLIANCE SEMICONDUCTOR CO LTD3 citations84
US9690511B2Jun 27, 2017
Multi-core data array power gating restoral mechanism
VIA ALLIANCE SEMICONDUCTOR CO LTD3 citations73
US9665490B2May 30, 2017
Apparatus and method for repairing cache arrays in a multi-core microprocessor
VIA ALLIANCE SEMICONDUCTOR CO LTD5 citations73
US9582428B2Feb 28, 2017
Multi-core programming apparatus and method for restoring data arrays following a power gating event
VIA ALLIANCE SEMICONDUCTOR CO LTD3 citations73
US9740622B2Aug 22, 2017
Extended fuse reprogrammability mechanism
VIA ALLIANCE SEMICONDUCTOR CO LTD0 citations63
US9727478B2Aug 8, 2017
Apparatus and method for configurable redundant fuse banks
VIA ALLIANCE SEMICONDUCTOR CO LTD0 citations63
US9727477B2Aug 8, 2017
Core-specific fuse mechanism for a multi-core die
VIA ALLIANCE SEMICONDUCTOR CO LTD0 citations63
US9715457B2Jul 25, 2017
Multi-core fuse decompression mechanism
VIA ALLIANCE SEMICONDUCTOR CO LTD0 citations63
US9710390B2Jul 18, 2017
Apparatus and method for extended cache correction
VIA ALLIANCE SEMICONDUCTOR CO LTD0 citations63
US9477608B2Oct 25, 2016
Apparatus and method for rapid fuse bank access in a multi-core processor
VIA ALLIANCE SEMICONDUCTOR CO LTD0 citations63
US9471502B2Oct 18, 2016
Multi-core microprocessor configuration data compression and decompression system
VIA ALLIANCE SEMICONDUCTOR CO LTD0 citations63
US9396123B2Jul 19, 2016
Core-specific fuse mechanism for a multi-core die
VIA ALLIANCE SEMICONDUCTOR CO LTD0 citations63
US9396124B2Jul 19, 2016
Apparatus and method for configurable redundant fuse banks
VIA ALLIANCE SEMICONDUCTOR CO LTD0 citations63
US9390022B2Jul 12, 2016
Apparatus and method for extended cache correction
VIA ALLIANCE SEMICONDUCTOR CO LTD0 citations63
US9384141B2Jul 5, 2016
Multi-core fuse decompression mechanism
VIA ALLIANCE SEMICONDUCTOR CO LTD0 citations63
US9384140B2Jul 5, 2016
Apparatus and method for storage and decompression of configuration data
VIA ALLIANCE SEMICONDUCTOR CO LTD0 citations63
US9378147B2Jun 28, 2016
Extended fuse reprogrammability mechanism
VIA ALLIANCE SEMICONDUCTOR CO LTD0 citations63
US9606933B2Mar 28, 2017
Multi-core apparatus and method for restoring data arrays following a power gating event
VIA ALLIANCE SEMICONDUCTOR CO LTD0 citations52
US9594690B2Mar 14, 2017
Multi-core microprocessor power gating cache restoral programming mechanism
VIA ALLIANCE SEMICONDUCTOR CO LTD0 citations52
US9594691B2Mar 14, 2017
Multi-core programming apparatus and method for restoring data arrays following a power gating event
VIA ALLIANCE SEMICONDUCTOR CO LTD0 citations52
US9582429B2Feb 28, 2017
Multi-core data array power gating cache restoral programming mechanism
VIA ALLIANCE SEMICONDUCTOR CO LTD0 citations52
US9524241B2Dec 20, 2016
Multi-core microprocessor power gating cache restoral mechanism
VIA ALLIANCE SEMICONDUCTOR CO LTD0 citations42
VIA TECH INC
6 patentsUS8879345B1Nov 4, 2014
Microprocessor mechanism for decompression of fuse correction data
VIA TECH INC71 citations98
US8982655B1Mar 17, 2015
Apparatus and method for compression and decompression of microprocessor configuration data
VIA TECH INC30 citations94
US7663957B2Feb 16, 2010
Microprocessor with program-accessible re-writable non-volatile state embodied in blowable fuses of the microprocessor
VIA TECH INC34 citations92
US9223715B2Dec 29, 2015
Microprocessor mechanism for decompression of cache correction data
VIA TECH INC0 citations63
US9395802B2Jul 19, 2016
Multi-core data array power gating restoral mechanism
VIA TECH INC1 citations52
US9348690B2May 24, 2016
Correctable configuration data compression and decompression system
VIA TECH INC0 citations42
IP FIRST LLC
4 patentsUS6189091B1Feb 13, 2001
Apparatus and method for speculatively updating global history and restoring same on branch misprediction detection
IP FIRST LLC53 citations96
US6609191B1Aug 19, 2003
Method and apparatus for speculative microinstruction pairing
IP FIRST LLC19 citations92
US6526502B1Feb 25, 2003
Apparatus and method for speculatively updating global branch history with branch prediction prior to resolution of branch outcome
IP FIRST LLC38 citations92
US6061781AMay 9, 2000
Concurrent execution of divide microinstructions in floating point unit and overflow detection microinstructions in integer unit for integer divide
IP FIRST LLC43 citations92
HENRY G GLENN
4 patentsUS8242800B2Aug 14, 2012
Apparatus and method for override access to a secured programmable fuse array
HENRY G GLENN29 citations92
US8341472B2Dec 25, 2012
Apparatus and method for tamper protection of a microprocessor fuse array
HENRY G GLENN4 citations63
US8281222B2Oct 2, 2012
Detection and correction of fuse re-growth in a microprocessor
HENRY G GLENN2 citations63
US8429471B2Apr 23, 2013
Microprocessor apparatus and method for securing a programmable fuse array
HENRY G GLENN1 citations52