Inventor

BHATTACHARYYA BINATA

US20 patents

⚠️ This page may combine multiple inventors who share the name “BHATTACHARYYA BINATA”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

BHATTACHARYYA BINATA

INTEL CORP

Avoiding deadlocks in a multiprocessor system

Quiescing and de-quiescing point-to-point links

Protect non-memory encryption engine (non-mee) metadata in trusted execution environment

Synchronizing control and data paths traversed by a data transaction

Techniques for memory access in a reduced power state

Supporting configurable security levels for memory address ranges

Supporting configurable security levels for memory address ranges

Efficient sharing of hardware encryption pipeline for multiple security solutions

Techniques for memory access in a reduced power state

Techniques for memory access in a reduced power state

Tree-less integrity and replay memory protection for trusted execution environment

Apparatus, method, and system for early deep sleep state exit of a processing element

Increasing turbo mode residency of a processor

Increasing turbo mode residency of a processor

Cache and data organization for memory protection

Implementation of reserved cache slots in computing system having inclusive/non inclusive tracking and two level system memory

Apparatus, method, and system for early deep sleep state exit of a processing element

GUDDETI JAYAKRISHNA

Increasing turbo mode residency of a processor

Apparatus, method, and system for early deep sleep state exit of a processing element

BHATTACHARYYA BINATA

Methods and tools to debug complex multi-core, multi-socket QPI based system