Inventor

MUKHERJEE SHUBHENDU SEKHAR

US52 patents

⚠️ This page may combine multiple inventors who share the name “MUKHERJEE SHUBHENDU SEKHAR”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

MUKHERJEE SHUBHENDU SEKHAR

MARVELL ASIA PTE LTD

Shared mid-level data cache

Vector prefetching for computing systems

Managing processor core synchronization using interrupts

History table management for a correlated prefetcher

Noisy instructions for side-channel attack mitigation

Managing prefetch lookahead distance based on memory access latency

Pipelines for secure multithread execution

Dynamic designation of instructions as sensitive for constraining multithreaded execution

Microarchitectural sensitive tag flow

Managing commit order for an external instruction relative to queued instructions

Dynamic designation of instructions as sensitive for constraining instruction execution

Pipelines for secure multithread execution

Managing out-of-order retirement of instructions based on received instructions indicating start or stop to out-of-order retirement

Prime and probe attack mitigation

Prime and probe attack mitigation

Managing out-of-order retirement of instructions

Managing power in an integrated circuit for high-speed activation

Managing power in an integrated circuit for high-speed activation

External way allocation circuitry for processor cores

CAVIUM INC

Managing synonyms in virtual-address caches

Managing memory access requests with prefetch for streams

Managing translation invalidation

Caching TLB translations using a unified page table walker cache

Managing address-independent page attributes

Translation lookaside buffer invalidation suppression

Managing buffered communication between cores

Managing buffered communication between sockets

Filtering translation lookaside buffer invalidations

Instruction ordering for in-progress operations

Managing reuse information with multiple translation stages

CAVIUM LLC

Managing cache partitions based on cache usage information

Managing fairness for lock and unlock operations using operation prioritization

Managing lock and unlock operations using active spinning

Managing virtual-address caches for multiple memory page sizes

Admission control for memory access requests

Local ordering of instructions in a computing system

Managing memory access requests with prefetch for streams

Managing lock and unlock operations using operation prediction

Managing lock and unlock operations using traffic prioritization

Instruction ordering for in-progress operations

Local instruction ordering based on memory domains

MARVELL INT LTD

Managing potential faults for speculative page table access

Managing commit order for an external instruction relative to two unissued queued instructions

Managing translation lookaside buffer entries based on associativity and page size

Managing predictor selection for branch prediction

Managing low-level instructions and core interactions in multi-core processors

MARVELL WORLD TRADE LTD

Managing load and store instructions for memory barrier handling

Managing branch prediction information for different contexts

Managing obscured branch prediction information

SIFIVE INC

Error management in system on a chip with securely partitioned memory space