Inventor
BERTONE MICHAEL
US18 patents
⚠️ This page may combine multiple inventors who share the name “BERTONE MICHAEL”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
CAVIUM LLC
6 patentsUS10331500B2Jun 25, 2019
Managing fairness for lock and unlock operations using operation prioritization
CAVIUM LLC4 citations72
US10248420B2Apr 2, 2019
Managing lock and unlock operations using active spinning
CAVIUM LLC2 citations72
US10223279B2Mar 5, 2019
Managing virtual-address caches for multiple memory page sizes
CAVIUM LLC3 citations72
US10599577B2Mar 24, 2020
Admission control for memory access requests
CAVIUM LLC2 citations69
US10599430B2Mar 24, 2020
Managing lock and unlock operations using operation prediction
CAVIUM LLC0 citations51
US10445096B2Oct 15, 2019
Managing lock and unlock operations using traffic prioritization
CAVIUM LLC0 citations51
CAVIUM INC
5 patentsUS9208103B2Dec 8, 2015
Translation bypass in multi-stage address translation
CAVIUM INC22 citations92
US9639476B2May 2, 2017
Merged TLB structure for multiple sequential address translations
CAVIUM INC15 citations84
US9268694B2Feb 23, 2016
Maintenance of cache and tags in a translation lookaside buffer
CAVIUM INC14 citations84
US9645941B2May 9, 2017
Collapsed address translation with multiple page sizes
CAVIUM INC10 citations82
US10042778B2Aug 7, 2018
Collapsed address translation with multiple page sizes
CAVIUM INC0 citations50
MARVELL INT LTD
4 patentsUS11176055B1Nov 16, 2021
Managing potential faults for speculative page table access
MARVELL INT LTD14 citations85
US10817300B2Oct 27, 2020
Managing commit order for an external instruction relative to two unissued queued instructions
MARVELL INT LTD2 citations72
US10846239B2Nov 24, 2020
Managing translation lookaside buffer entries based on associativity and page size
MARVELL INT LTD1 citations62
US11327759B2May 10, 2022
Managing low-level instructions and core interactions in multi-core processors
MARVELL INT LTD0 citations49