Inventor
OGURA MITSUGI
JP23 patents
⚠️ This page may combine multiple inventors who share the name “OGURA MITSUGI”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
TOSHIBA KK
14 patentsUS4630088ADec 16, 1986
MOS dynamic ram
TOSHIBA KK139 citations98
US4706249ANov 10, 1987
Semiconductor memory device having error detection/correction function
TOSHIBA KK72 citations96
US5942784AAug 24, 1999
Semiconductor device
TOSHIBA KK38 citations92
US4799193AJan 17, 1989
Semiconductor memory devices
TOSHIBA KK33 citations92
US4748596AMay 31, 1988
Semiconductor memory device with sense amplifiers
TOSHIBA KK27 citations92
US4992389AFeb 12, 1991
Making a self aligned semiconductor device
TOSHIBA KK36 citations91
US4688064AAug 18, 1987
Dynamic memory cell and method for manufacturing the same
TOSHIBA KK19 citations82
US5635850AJun 3, 1997
Intelligent test line system
TOSHIBA KK13 citations74
US4798794AJan 17, 1989
Method for manufacturing dynamic memory cell
TOSHIBA KK6 citations74
US4725985AFeb 16, 1988
Circuit for applying a voltage to a memory cell MOS capacitor of a semiconductor memory device
TOSHIBA KK10 citations74
US5227319AJul 13, 1993
Method of manufacturing a semiconductor device
TOSHIBA KK7 citations72
US4881113ANov 14, 1989
Semiconductor integrated circuits with a protection device
TOSHIBA KK8 citations70
US9627658B2Apr 18, 2017
Battery and battery pack
TOSHIBA KK3 citations67
US5095463AMar 10, 1992
Semiconductor memory device
TOSHIBA KK4 citations63
TOKYO SHIBAURA ELECTRIC CO
8 patentsUS4636981AJan 13, 1987
Semiconductor memory device having a voltage push-up circuit
TOKYO SHIBAURA ELECTRIC CO68 citations96
US4763178AAug 9, 1988
Semiconductor memory device
TOKYO SHIBAURA ELECTRIC CO18 citations74
US4564854AJan 14, 1986
Combined MOS/memory transistor structure
TOKYO SHIBAURA ELECTRIC CO8 citations74
US4433911AFeb 28, 1984
Method of evaluating measure precision of patterns and photomask therefor
TOKYO SHIBAURA ELECTRIC CO17 citations74
US4644184AFeb 17, 1987
Memory clock pulse generating circuit with reduced peak current requirements
TOKYO SHIBAURA ELECTRIC CO16 citations73
US4492973AJan 8, 1985
MOS Dynamic memory cells and method of fabricating the same
TOKYO SHIBAURA ELECTRIC CO4 citations63
US4490628ADec 25, 1984
MOS Decoder selection circuit having a barrier transistor whose non-conduction period is unaffected by substrate potential disturbances
TOKYO SHIBAURA ELECTRIC CO3 citations63
US4611237ASep 9, 1986
Semiconductor integrated circuit device
TOKYO SHIBAURA ELECTRIC CO2 citations62