Inventor
MORESCO LARRY LOUIS
US8 patents
Patents
8 patentsUS5722162AMar 3, 1998
Fabrication procedure for a stable post
FUJITSU LTD97 citations97
US6733685B2May 11, 2004
Methods of planarizing structures on wafers and substrates by polishing
FUJITSU LTD64 citations96
US6034332AMar 7, 2000
Power supply distribution structure for integrated circuit chip modules
FUJITSU LTD47 citations96
US5773889AJun 30, 1998
Wire interconnect structures for connecting an integrated circuit to a substrate
FUJITSU LTD162 citations95
US5334804AAug 2, 1994
Wire interconnect structures for connecting an integrated circuit to a substrate
FUJITSU LTD280 citations95
US5916453AJun 29, 1999
Methods of planarizing structures on wafers and substrates by polishing
FUJITSU LTD38 citations92
US5765279AJun 16, 1998
Methods of manufacturing power supply distribution structures for multichip modules
FUJITSU LTD20 citations92
US5930890AAug 3, 1999
Structure and fabrication procedure for a stable post
FUJITSU LTD12 citations73