Inventor

LIU LAWRENCE C

US10 patents

⚠️ This page may combine multiple inventors who share the name “LIU LAWRENCE C”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

MOSEL VITELIC CORP

9 patents

US5757710AMay 26, 1998

DRAM with edge sense amplifiers which are activated along with sense amplifiers internal to the array during a read cycle

MOSEL VITELIC CORP30 citations92

US5844296ADec 1, 1998

Space saving laser programmable fuse layout

MOSEL VITELIC CORP17 citations84

US6011737AJan 4, 2000

DRAM with edge sense amplifiers which are activated along with sense amplifiers internal to the array during a read cycle

MOSEL VITELIC CORP7 citations73

US5966338AOct 12, 1999

Dram with new I/O data path configuration

MOSEL VITELIC CORP7 citations73

US5912571AJun 15, 1999

Using the internal supply voltage ramp rate to prevent premature enabling of a device during power-up

MOSEL VITELIC CORP14 citations73

US5781488AJul 14, 1998

Simulated DRAM memory bit line/bit line for circuit timing and voltage level tracking

MOSEL VITELIC CORP2 citations62

MOSEL VITALIC CORP

1 patent

US5838072ANov 17, 1998

Intrachip power distribution package and method for semiconductors having a supply node electrically interconnected with one or more intermediate nodes

MOSEL VITALIC CORP75 citations93

LIU LAWRENCE C

MOSEL VITELIC CORP

DRAM with edge sense amplifiers which are activated along with sense amplifiers internal to the array during a read cycle

Space saving laser programmable fuse layout

DRAM with edge sense amplifiers which are activated along with sense amplifiers internal to the array during a read cycle

Dram with new I/O data path configuration

Using the internal supply voltage ramp rate to prevent premature enabling of a device during power-up

DRAM with new I/O data path configuration

Charge storage for sensing operations in a DRAM

Reconfigurable multiplexed address scheme for asymmetrically addressed DRAMs

Simulated DRAM memory bit line/bit line for circuit timing and voltage level tracking

MOSEL VITALIC CORP

Intrachip power distribution package and method for semiconductors having a supply node electrically interconnected with one or more intermediate nodes