Inventor
CHO SHIZUO
JP13 patents
Patents
13 patentsUS5337278AAug 9, 1994
Low-power decoder for selecting redundant memory cells
OKI ELECTRIC IND CO LTD23 citations92
US5161121ANov 3, 1992
Random access memory including word line clamping circuits
OKI ELECTRIC IND CO LTD54 citations92
US5148399ASep 15, 1992
Sense amplifier circuitry selectively separable from bit lines for dynamic random access memory
OKI ELECTRIC IND CO LTD22 citations92
US5357468AOct 18, 1994
Semiconductor memory device
OKI ELECTRIC IND CO LTD35 citations91
US5140556AAug 18, 1992
Semiconductor memory circuit having dummy cells connected to twisted bit lines
OKI ELECTRIC IND CO LTD28 citations91
US5103158AApr 7, 1992
Reference voltage generating circuit
OKI ELECTRIC IND CO LTD21 citations81
US6593795B2Jul 15, 2003
Level adjustment circuit and data output circuit thereof
OKI ELECTRIC IND CO LTD10 citations73
US6459322B1Oct 1, 2002
Level adjustment circuit and data output circuit thereof
OKI ELECTRIC IND CO LTD8 citations73
US5510750AApr 23, 1996
Bias circuit for providing a stable output current
OKI ELECTRIC IND CO LTD14 citations73
US5369320ANov 29, 1994
Bootstrapped high-speed output buffer
OKI ELECTRIC IND CO LTD17 citations72
US5058073AOct 15, 1991
CMOS RAM having a complementary channel sense amplifier
OKI ELECTRIC IND CO LTD15 citations72
US5001669AMar 19, 1991
Semiconductor memory circuit having dummy cells connected to twisted bit lines
OKI ELECTRIC IND CO LTD15 citations72
US6337815B1Jan 8, 2002
Semiconductor memory device having redundant circuit
OKI ELECTRIC IND CO LTD6 citations62