Inventor
NEYRET ERIC
FR24 patents
⚠️ This page may combine multiple inventors who share the name “NEYRET ERIC”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
SOITEC SILICON ON INSULATOR
19 patentsUS6962858B2Nov 8, 2005
Method for reducing free surface roughness of a semiconductor wafer
SOITEC SILICON ON INSULATOR45 citations92
US6853802B2Feb 8, 2005
Heat treatment for edges of multilayer semiconductor wafers
SOITEC SILICON ON INSULATOR24 citations92
US7405136B2Jul 29, 2008
Methods for manufacturing compound-material wafers and for recycling used donor substrates
SOITEC SILICON ON INSULATOR25 citations91
US7081399B2Jul 25, 2006
Method for producing a high quality useful layer on a substrate utilizing helium and hydrogen implantations
SOITEC SILICON ON INSULATOR14 citations84
US6939783B2Sep 6, 2005
Preventive treatment method for a multilayer semiconductor wafer
SOITEC SILICON ON INSULATOR13 citations84
US6903032B2Jun 7, 2005
Method for preparing a semiconductor wafer surface
SOITEC SILICON ON INSULATOR13 citations84
US7514341B2Apr 7, 2009
Finishing process for the manufacture of a semiconductor structure
SOITEC SILICON ON INSULATOR8 citations83
US7190029B2Mar 13, 2007
Preventive treatment method for a multilayer semiconductor wafer
SOITEC SILICON ON INSULATOR6 citations74
US7863158B2Jan 4, 2011
Treatment for bonding interface stabilization
SOITEC SILICON ON INSULATOR3 citations63
US7285471B2Oct 23, 2007
Process for transfer of a thin layer formed in a substrate with vacancy clusters
SOITEC SILICON ON INSULATOR6 citations63
US7049250B2May 23, 2006
Heat treatment for edges of multilayer semiconductor wafers
SOITEC SILICON ON INSULATOR2 citations63
US7883628B2Feb 8, 2011
Method of reducing the surface roughness of a semiconductor wafer
SOITEC SILICON ON INSULATOR4 citations62
US7749910B2Jul 6, 2010
Method of reducing the surface roughness of a semiconductor wafer
SOITEC SILICON ON INSULATOR2 citations62
US7666758B2Feb 23, 2010
Process for fabricating a substrate of the silicon-on-insulator type with thin surface layer
SOITEC SILICON ON INSULATOR2 citations62
US7485545B2Feb 3, 2009
Method of configuring a process to obtain a thin layer with a low density of holes
SOITEC SILICON ON INSULATOR4 citations62
US7138344B2Nov 21, 2006
Method for minimizing slip line faults on a semiconductor wafer surface
SOITEC SILICON ON INSULATOR3 citations62
US7001832B2Feb 21, 2006
Method for limiting slip lines in a semiconductor substrate
SOITEC SILICON ON INSULATOR2 citations62
US7939427B2May 10, 2011
Process for fabricating a substrate of the silicon-on-insulator type with reduced roughness and uniform thickness
SOITEC SILICON ON INSULATOR2 citations60
US7947571B2May 24, 2011
Method for fabricating a semiconductor on insulator substrate with reduced Secco defect density
SOITEC SILICON ON INSULATOR0 citations39
NEYRET ERIC
3 patentsUS8461018B2Jun 11, 2013
Treatment for bonding interface stabilization
NEYRET ERIC0 citations49
US8273636B2Sep 25, 2012
Process for the transfer of a thin layer formed in a substrate with vacancy clusters
NEYRET ERIC1 citations49
US8216916B2Jul 10, 2012
Treatment for bonding interface stabilization
NEYRET ERIC0 citations49