Inventor

CHAKRAVARTY SREEJIT

US23 patents

⚠️ This page may combine multiple inventors who share the name “CHAKRAVARTY SREEJIT”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

CHAKRAVARTY SREEJIT

CHAKRAVARTY SREEJIT

System and method for testing memory power management modes in an integrated circuit

Victim port-based design for test area overhead reduction in multiport latch-based memories

Logic BIST for system testing using stored patterns

Critical path monitor for an integrated circuit and method of operation thereof

Electronic design automation tool and method for employing unsensitized critical path information to reduce leakage power in an integrated circuit

Low cost comparator design for memory BIST

Test technique to apply a variable scan clock including a scan clock modifier on an integrated circuit

Low-cost design for register file testability

Scan cell designs with serial and parallel loading of test data

INTEL CORP

Scaleable approach to extracting bridges from a hierarchically described VLSI layout

In-field system test security

Methods, systems and apparatus for in-field testing for generic diagnostic components

Test architecture for die to die interconnect for three dimensional integrated circuits

In-field system testing

Method and apparatus for extracting bridges from an integrated circuit layout

Method and apparatus for extracting bridges from an integrated circuit layout

LSI CORP

Data transformations to improve ROM yield and programming time

Stored-pattern logic self-testing with serial communication

System and method for reducing the generation of inconsequential violations resulting from timing analyses

Electronic design automation tool and method for optimizing the placement of process monitors in an integrated circuit

Enhanced logic built-in self-test module and method of online system testing employing the same

TETELBAUM ALEXANDER

Timing error sampling generator, critical path monitor for hold and setup violations of an integrated circuit and a method of timing testing

Timing error sampling generator and a method of timing testing