Inventor

KIM JUNG PILL

US153 patents

⚠️ This page may combine multiple inventors who share the name “KIM JUNG PILL”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

KIM JUNG PILL

QUALCOMM INC

System and method to trim reference levels in a resistive memory

Sense amplifier offset voltage reduction

Systems and methods to refresh DRAM based on temperature and based on calibration data

System, apparatus, and method for sense amplifiers

Kernel masking of DRAM defects

Memory cell that includes multiple non-volatile memories

Offset-cancellation sensing circuit (OCSC)-based non-volatile (NV) memory circuits

Data bit inversion tracking in cache memory to reduce data bits written for write operations

Magnetoresistive (MR) sensors employing dual MR devices for differential MR sensing

Method and apparatus for refreshing a memory cell

Voltage self-boosting circuit for generating a boosted voltage for driving a word line write in a memory array for a memory write operation

Write driver circuits for resistive random access memory (RAM) arrays

Systems and methods for recovering from uncorrected DRAM bit errors

MRAM initialization devices and methods

System and method of sensing a memory cell

System and method to provide a reference cell using magnetic tunnel junction cells

Read operation of MRAM using a dummy word line

System and method to trim reference levels in a resistive memory

Magnetic random access memory (MRAM)layout with uniform pattern

INFINEON TECHNOLOGIES AG

Method and apparatus compensating for frequency drift in a delay locked loop

Internal voltage generator with temperature control

Back-bias voltage generator with temperature control

Temperature sensor scheme

Method and circuit configuration for multiple charge recycling during refresh operations in a DRAM device

Latch scheme with invalid command detector

Temperature compensated delay signals

Duty cycle corrector

KIM JUNG PILL

OTP cell with reversed MTJ connection

OTP scheme with multiple magnetic tunnel junction devices in a cell

Reference cell repair scheme

System and method for shared sensing MRAM

Non-volatile memory array configurable for high performance and high density

Reference cell write operations at a memory

System and method of reference cell testing

HYUNDAI ELECTRONICS IND

Semiconductor device for automatically detecting external interface voltage

Differential amplifier with reduced current consumption

Automatic mode selection circuit for semiconductor memory device

Method for driving word lines in semiconductor memory device

RAO HARI M

Generating a non-reversible state at a bitcell having a first magnetic tunnel junction and a second magnetic tunnel junction

Multi-port non-volatile memory that includes a resistive memory element

Programmable write driver for STT-MRAM

QUALCOMM TECHNOLOGIES INC

Metal-oxide semiconductor (MOS) transistor offset-cancelling (OC), zero-sensing (ZS) dead zone, current-latched sense amplifiers (SAs) (CLSAs) (OCZS-SAs) for sensing differential voltages

Non-volatile (NV)-content addressable memory (CAM) (NV-CAM) cells employing differential magnetic tunnel junction (MTJ) sensing for increased sense margin

ZHU XIAOCHUN

Asymmetric write scheme for magnetic bit cell elements

Circuit and method for generating a reference level for a magnetic random access memory element

QIMONDA NORTH AMERICA CORP

Self-diagnostic scheme for detecting errors

HAO WUYANG

Method and apparatus to provide a clock signal to a charge pump

LI XIA

MTP MTJ device

LEE KANGHO

Magnetic random access memory (MRAM) layout with uniform pattern

JUNG SEONG-OOK

Latching circuit