Inventor
CHOI JOONYOUNG
KR15 patents
⚠️ This page may combine multiple inventors who share the name “CHOI JOONYOUNG”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
CHOI JOONYOUNG
4 patentsUS8835301B2Sep 16, 2014
Semiconductor device and method of forming bump structure with insulating buffer layer to reduce stress on semiconductor wafer
CHOI JOONYOUNG5 citations82
US8994048B2Mar 31, 2015
Semiconductor device and method of forming recesses in substrate for same size or different sized die with vertical integration
CHOI JOONYOUNG4 citations71
US8546194B2Oct 1, 2013
Integrated circuit packaging system with interconnects and method of manufacture thereof
CHOI JOONYOUNG6 citations70
US9093278B1Jul 28, 2015
Method of manufacture of integrated circuit packaging system with plasma processing
CHOI JOONYOUNG0 citations50
SAMSUNG ELECTRONICS CO LTD
3 patentsUS11171038B2Nov 9, 2021
Fabrication method of integrated circuit semiconductor device
SAMSUNG ELECTRONICS CO LTD0 citations62
US11888038B2Jan 30, 2024
Integrated circuit devices and methods of manufacturing the same
SAMSUNG ELECTRONICS CO LTD0 citations61
US8343853B2Jan 1, 2013
Semiconductor wafer, semiconductor device using the same, and method and apparatus for producing the same
SAMSUNG ELECTRONICS CO LTD1 citations48
STATS CHIPPAC LTD
3 patentsUS9780063B2Oct 3, 2017
Semiconductor device and method of forming bump structure with insulating buffer layer to reduce stress on semiconductor wafer
STATS CHIPPAC LTD1 citations51
US9524958B2Dec 20, 2016
Semiconductor device and method of individual die bonding followed by simultaneous multiple die thermal compression bonding
STATS CHIPPAC LTD1 citations49
US9252093B2Feb 2, 2016
Semiconductor device and method of forming multi-layered UBM with intermediate insulating buffer layer to reduce stress for semiconductor wafer
STATS CHIPPAC LTD0 citations49