Inventor
SADASIVAM SATISH K
IN22 patents
⚠️ This page may combine multiple inventors who share the name “SADASIVAM SATISH K”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
IBM
16 patentsUS10528349B2Jan 7, 2020
Branch synthetic generation across multiple microarchitecture generations
IBM16 citations93
US9921836B2Mar 20, 2018
Branch synthetic generation across multiple microarchitecture generations
IBM3 citations72
US9229746B2Jan 5, 2016
Identifying load-hit-store conflicts
IBM3 citations71
US10241834B2Mar 26, 2019
Bandwidth aware resource optimization
IBM2 citations68
US9753776B2Sep 5, 2017
Simultaneous multithreading resource sharing
IBM2 citations68
US9519481B2Dec 13, 2016
Branch synthetic generation across multiple microarchitecture generations
IBM1 citations62
US8930760B2Jan 6, 2015
Validating cache coherency protocol within a processor
IBM2 citations61
US8892949B2Nov 18, 2014
Effective validation of execution units within a processor
IBM2 citations61
US9104577B2Aug 11, 2015
Optimizing memory bandwidth consumption using data splitting with software caching
IBM3 citations59
US10929184B2Feb 23, 2021
Bandwidth aware resource optimization
IBM0 citations57
US9886274B2Feb 6, 2018
Branch synthetic generation across multiple microarchitecture generations
IBM0 citations51
US9542183B2Jan 10, 2017
Branch synthetic generation across multiple microarchitecture generations
IBM0 citations51
US9158640B2Oct 13, 2015
Tightly-coupled context-aware irritator thread creation for verification of microprocessors
IBM0 citations51
US9021281B2Apr 28, 2015
Run-time task-level dynamic energy management
IBM1 citations48
US9928068B2Mar 27, 2018
Hardware managed dynamic thread fetch rate control
IBM1 citations47
US10838871B2Nov 17, 2020
Hardware processor architecture having a hint cache
IBM0 citations41