Inventor

WANG CHIEN-JUNG

TW36 patents

⚠️ This page may combine multiple inventors who share the name “WANG CHIEN-JUNG”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

WANG CHIEN-JUNG

TAIWAN SEMICONDUCTOR MFG

Flexible metal-oxide-metal capacitor design

Test structure for detecting bridging of DRAM capacitors

Seal ring structures with reduced moisture-induced reliability degradation

Method and apparatus for stress testing integrated circuits using an adjustable AC hot carrier injection source

Method for forming a borderless contact

Seal ring structures with reduced moisture-induced reliability degradation

Interconnect structure to reduce stress induced voiding effect

Test structure and related methods for evaluating stress-induced voiding

Test structure with TDDB test pattern

Interconnect structure to reduce stress induced voiding effect

Method of protecting tungsten plug from corroding

Wiring structure to minimize stress induced void formation

Method for measuring a property of interconnections and structure for the same

Fabrication method of a device isolation structure

Metal oxide metal capacitor with slot vias

Method of forming via

Method of forming an interconnect structure having an enlarged region

Interconnect structure to reduce stress induced voiding effect

Test structure for speeding a stress-induced voiding test and method of using same

Test structure for detecting bridging of DRAM capacitors

TAIWAN SEMICONDUCTOR MFG CO LTD

Semiconductor structure and manufacturing method thereof

Semiconductor structure and manufacturing method thereof

Semiconductor structure and manufacturing method thereof

Semiconductor structure and manufacturing method thereof

Method of forming bandgap reference integrated circuit

Circuit with a droop compensating mechanism

Bandgap reference circuit

MiM capacitor

WANG CHIEN-JUNG

Seal ring structures with reduced moisture-induced reliability degradation

Interconnect structure to reduce stress induced voiding effect

Method of forming an interconnect structure having an enlarged region

WORLDWIDE SEMICONDUCTOR MANUFA

Alignment-marker structure and method of forming the same in integrated circuit fabrication

WORLDWIDE SEMICONDUCTOR MFG

Method for forming a planar intermetal dielectric using a barrier layer

TAIWAN SEMICONDUCTOR MFG CORP

Semiconductor device comprising a test structure

WISTRON NEWEB CORP

Waterproof device

WANG CHIN-SHAN

Metal oxide metal capacitor with slot vias