Inventor
THATCHER LARRY EDWARD
US23 patents
⚠️ This page may combine multiple inventors who share the name “THATCHER LARRY EDWARD”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
IBM
20 patentsUS6021485AFeb 1, 2000
Forwarding store instruction result to load instruction with reduced stall or flushing by effective/real data address bytes matching
IBM113 citations98
US6543002B1Apr 1, 2003
Recovery from hang condition in a microprocessor
IBM55 citations96
US6266768B1Jul 24, 2001
System and method for permitting out-of-order execution of load instructions
IBM63 citations96
US6237081B1May 22, 2001
Queuing method and apparatus for facilitating the rejection of sequential instructions in a processor
IBM81 citations96
US6336183B1Jan 1, 2002
System and method for executing store instructions
IBM71 citations95
US6477635B1Nov 5, 2002
Data processing system including load/store unit having a real address tag array and method for correcting effective address aliasing
IBM25 citations92
US6338128B1Jan 8, 2002
System and method for invalidating an entry in a translation unit
IBM24 citations92
US6336168B1Jan 1, 2002
System and method for merging multiple outstanding load miss instructions
IBM46 citations92
US6085289AJul 4, 2000
Method and system for load data formatting and improved method for cache line organization
IBM29 citations92
US5931957AAug 3, 1999
Support for out-of-order execution of loads and stores in a processor
IBM57 citations92
US6901540B1May 31, 2005
TLB parity error recovery
IBM42 citations90
US6301654B1Oct 9, 2001
System and method for permitting out-of-order execution of load and store instructions
IBM34 citations89
US6298436B1Oct 2, 2001
Method and system for performing atomic memory accesses in a processor system
IBM18 citations84
US6289428B1Sep 11, 2001
Superscaler processor and method for efficiently recovering from misaligned data addresses
IBM16 citations84
US6658555B1Dec 2, 2003
Determining successful completion of an instruction by comparing the number of pending instruction cycles with a number based on the number of stages in the pipeline
IBM12 citations74
US6021467AFeb 1, 2000
Apparatus and method for processing multiple cache misses to a single cache line
IBM13 citations74
US6425069B1Jul 23, 2002
Optimization of instruction stream execution that includes a VLIW dispatch group
IBM10 citations73
US6079002AJun 20, 2000
Dynamic expansion of execution pipeline stages
IBM9 citations71
US5974259AOct 26, 1999
Data processing system and method of operation having input/output drivers with reduced power consumption and noise levels
IBM8 citations71
US6490653B1Dec 3, 2002
Method and system for optimally issuing dependent instructions based on speculative L2 cache hit in a data processing system
IBM4 citations62
INTEL CORP
3 patentsUS6678807B2Jan 13, 2004
System and method for multiple store buffer forwarding in a system with a restrictive memory model
INTEL CORP26 citations91
US6611900B2Aug 26, 2003
System and method for high performance execution of locked memory instructions in a system with distributed memory and a restrictive memory model
INTEL CORP19 citations91
US6463511B2Oct 8, 2002
System and method for high performance execution of locked memory instructions in a system with distributed memory and a restrictive memory model
INTEL CORP27 citations91