Inventor
HART MICHAEL J
US71 patents
⚠️ This page may combine multiple inventors who share the name “HART MICHAEL J”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
XILINX INC
34 patentsUS6777978B2Aug 17, 2004
Structures and methods for selectively applying a well bias to portions of a programmable device
XILINX INC125 citations99
US6621325B2Sep 16, 2003
Structures and methods for selectively applying a well bias to portions of a programmable device
XILINX INC90 citations98
US6268639B1Jul 31, 2001
Electrostatic-discharge protection circuit
XILINX INC64 citations96
US5970372AOct 19, 1999
Method of forming multilayer amorphous silicon antifuse
XILINX INC46 citations95
US5726484AMar 10, 1998
Multilayer amorphous silicon antifuse
XILINX INC61 citations95
US7504854B1Mar 17, 2009
Regulating unused/inactive resources in programmable logic devices for static power reduction
XILINX INC29 citations93
US7089527B2Aug 8, 2006
Structures and methods for selectively applying a well bias to portions of a programmable device
XILINX INC15 citations93
US6949951B1Sep 27, 2005
Integrated circuit multiplexer including transistors of more than one oxide thickness
XILINX INC21 citations93
US6768335B1Jul 27, 2004
Integrated circuit multiplexer including transistors of more than one oxide thickness
XILINX INC21 citations93
US6243294B1Jun 5, 2001
Memory architecture for non-volatile storage using gate breakdown structure in standard sub 0.35 micron process
XILINX INC25 citations93
US9575111B1Feb 21, 2017
On chip detection of electrical overstress events
XILINX INC20 citations92
US6645802B1Nov 11, 2003
Method of forming a zener diode
XILINX INC20 citations92
US6549458B1Apr 15, 2003
Non-volatile memory array using gate breakdown structures
XILINX INC25 citations92
US6522582B1Feb 18, 2003
Non-volatile memory array using gate breakdown structures
XILINX INC20 citations92
US7109734B2Sep 19, 2006
Characterizing circuit performance by separating device and interconnect impact on signal delay
XILINX INC18 citations91
US5870327AFeb 9, 1999
Mixed mode RAM/ROM cell using antifuses
XILINX INC25 citations91
US7544968B1Jun 9, 2009
Non-volatile memory cell with charge storage element and method of programming
XILINX INC8 citations84
US6982451B1Jan 3, 2006
Single event upset in SRAM cells in FPGAs with high resistivity gate structures
XILINX INC15 citations84
US6438065B1Aug 20, 2002
Redundancy architecture and method for non-volatile storage
XILINX INC14 citations84
US9484919B1Nov 1, 2016
Selection of logic paths for redundancy
XILINX INC7 citations83
US9281807B1Mar 8, 2016
Master-slave flip-flops and methods of implementing master-slave flip-flops in an integrated circuit
XILINX INC12 citations83
US10289178B1May 14, 2019
Configurable single event latch-up (SEL) and electrical overvoltage stress (EOS) detection circuit
XILINX INC11 citations82
US7793238B1Sep 7, 2010
Method and apparatus for improving a circuit layout using a hierarchical layout description
XILINX INC10 citations80
US7888771B1Feb 15, 2011
E-fuse with scalable filament link
XILINX INC7 citations79
US5768179AJun 16, 1998
Antifuse load sram cell
XILINX INC7 citations74
US11177654B1Nov 16, 2021
Electro-static discharge (ESD) damage self-test
XILINX INC2 citations73
US10962588B1Mar 30, 2021
Integrated circuit devices and methods of designing and producing integrated circuits
XILINX INC2 citations73
US9628081B2Apr 18, 2017
Interconnect circuits having low threshold voltage P-channel transistors for a programmable integrated circuit
XILINX INC4 citations73
US8351248B1Jan 8, 2013
CMOS SRAM memory cell with improved N/P current ratio
XILINX INC6 citations73
US5786240AJul 28, 1998
Method for over-etching to improve voltage distribution
XILINX INC15 citations73
US7724016B2May 25, 2010
Characterizing circuit performance by separating device and interconnect impact on signal delay
XILINX INC6 citations72
US7489152B2Feb 10, 2009
Characterizing circuit performance by separating device and interconnect impact on signal delay
XILINX INC7 citations72
US9825632B1Nov 21, 2017
Circuit for and method of preventing multi-bit upsets induced by single event transients
XILINX INC3 citations71
US10033388B1Jul 24, 2018
Circuit for and method of enabling the selection of a circuit
XILINX INC4 citations70
HART MICHAEL J
6 patentsUS8692381B1Apr 8, 2014
Integrated circuits with a resistance to single event upset occurrence and methods for providing the same
HART MICHAEL J12 citations84
US8519483B1Aug 27, 2013
Semiconductor device having a high resistance to ionizing radiation
HART MICHAEL J7 citations84
US8261229B2Sep 4, 2012
Method and apparatus for interconnect layout in an integrated circuit
HART MICHAEL J16 citations84
US9058853B2Jun 16, 2015
Integrated circuit having improved radiation immunity
HART MICHAEL J4 citations73
US8981491B1Mar 17, 2015
Memory array having improved radiation immunity
HART MICHAEL J6 citations73
US8410605B2Apr 2, 2013
Extended under-bump metal layer for blocking alpha particles in a semiconductor device
HART MICHAEL J5 citations73
NAT SEMICONDUCTOR CORP
3 patentsUS5108939AApr 28, 1992
Method of making a non-volatile memory cell utilizing polycrystalline silicon spacer tunnel region
NAT SEMICONDUCTOR CORP68 citations95
US5293331AMar 8, 1994
High density EEPROM cell with tunnel oxide stripe
NAT SEMICONDUCTOR CORP34 citations93
US5455790AOct 3, 1995
High density EEPROM cell array which can selectively erase each byte of data in each row of the array
NAT SEMICONDUCTOR CORP29 citations92
KARP JAMES
2 patentsGOOGLE INC
2 patentsWU YUN
1 patent(unassigned)
1 patentRAHMAN ARIFUR
1 patentShowing the top 50 of 71 patents by PatentIndex Score.