Inventor

HSU FU-CHIEH

US67 patents

⚠️ This page may combine multiple inventors who share the name “HSU FU-CHIEH”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

HSU FU-CHIEH

MONOLITHIC SYSTEM TECH INC

Method of fabricating a one transistor floating-body DRAM cell in bulk CMOS process with electrically isolated charge storage region

Memory array with read/write methods

Vertical one-transistor floating-body DRAM cell in bulk CMOS process with electrically isolated charge storage region

One-transistor floating-body DRAM cell in bulk CMOS process with electrically isolated charge storage region

Dynamic address mapping and redundancy in a modular memory device

Method and apparatus for complete hiding of the refresh of a semiconductor memory

Circuit module redundancy architecture process

Method and structure for implementing a cache memory using a DRAM array

Fault-tolerant hierarchical bus system and method of operating same

Resynchronization circuit for a memory system and method of operating same

Pseudo-nonvolatile memory incorporating data refresh operation

Circuit module redundancy architecture

Reduced CMOS-swing clamping circuit for bus lines

DRAM cell having a capacitor structure fabricated partially in a cavity and method for operating same

Termination circuit with power-down mode for use in circuit module architecture

Method of fabricating vertical one-transistor floating-body DRAM cell in bulk CMOS process with electrically isolated charge storage region

DRAM cell having a capacitor structure fabricated partially in a cavity and method for operating same

Memory modules with high speed latched sense amplifiers

Reduced topography DRAM cell fabricated using a modified logic process and method for operating same

High-density ratio-independent four-transistor RAM cell fabricated with a conventional logic process

Method of operating memory array with write buffers and related apparatus

Data processing system with master and slave devices and asymmetric signal swing bus

On-chip word line voltage generation for DRAM embedded in logic process

System utilizing a DRAM array as a next level cache memory and method for operating same

Termination circuits for reduced swing signal lines and methods for operating same

Method and circuit for communication between a module and a bus controller in a wafer-scale integrated circuit system

Defect tolerant integrated circuit subsystem for communication between a module and a bus controller in a wafer-scale integrated circuit system

Wafer-scale integrated circuit interconnect structure architecture

Error correcting memory and method of operating same

Non-volatile memory cell fabricated with slight modification to a conventional logic process and methods of operating same

Method of fabricating a DRAM cell having a thin dielectric access transistor and a thick dielectric storage

DRAM cell having a capacitor structure fabricated partially in a cavity and method for operating same

Non-volatile memory embedded in a conventional logic process

DRAM cell fabricated using a modified logic process and method for operating same

Apparatus for controlling data transfer between a bus and memory array and method for operating same

Method of operating a system-on-a-chip including entering a standby state in a non-volatile memory while operating the system-on-a-chip from a volatile memory

Method and structure of ternary CAM cell in logic process

Non-volatile memory cell and methods of fabricating and operating same

Memory cell for DRAM embedded in logic

Method and structure for improving display data bandwidth in a unified memory architecture system

Resynchronization circuit for circuit module architecture

INTEGRATED DEVICE TECH

Static ram cell with trench pull-down transistors and buried-layer ground plate

Method of making a static ram cell with trench pull-down transistors and buried-layer ground plate

Static random access memory cell using a P/N-MOS transistors

MONOLITHIC SYSTEMS INC

Multi-port DRAM cell and memory system using same

MONOLITHIC SYSTEM TECHNOLOGY

High density SRAM circuit with single-ended memory cells

MYSON TECHNOLOGY INC

Programmable antifuse structure, process, logic cell and architecture for programmable integrated circuits

HEWLETT PACKARD CO

Process for forming lightly-doped-drain (LDD) without extra masking steps

MOSYS INC

Error detection/correction method

KNIGHTS TECHNOLOGY INC

Contact sensing for integrated circuit testing