Inventor

QURESHI MOINUDDIN K

US23 patents

⚠️ This page may combine multiple inventors who share the name “QURESHI MOINUDDIN K”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

QURESHI MOINUDDIN K

IBM

Iterative write pausing techniques to improve read latency of memory systems

Adaptive wear leveling via monitoring the properties of memory reference stream

DRAM error detection, evaluation, and correction

DRAM error detection, evaluation, and correction

Managing errors in a DRAM by weak cell encoding

Out-of-place presetting based on indirection table

Probabilistic associative cache

Managing errors in a DRAM by weak cell encoding

BOSE PRADIP

Adaptive workload based optimizations to mitigate current delivery limitations in integrated circuits

Token-based current control to mitigate current delivery limitations in integrated circuits

Adaptive workload based optimizations coupled with a heterogeneous current-aware baseline design to mitigate current delivery limitations in integrated circuits

Measuring data switching activity in a microprocessor

Current-aware floorplanning to overcome current delivery limitations in integrated circuits

FRANCESCHINI MICHELE M

Memory cell presetting for improved memory performance

Method for optimizing refresh rate for DRAM

DRAM refresh

Adaptive wear leveling via monitoring the properties of memory reference stream

EMMA PHILIP G

Processor core stacking for efficient collaboration

BERNSTEIN KERRY

Adaptive linesize in a cache

INTEL CORP

Demand-based error correction

QURESHI MOINUDDIN K

Adaptive spill-receive mechanism for lateral caches

ABALI BULENT

Probabilistic associative cache

FRANCESCHINI MICHELE

Variability aware wear leveling