Inventor

PENG CHAO-HSIEN

TW30 patents

⚠️ This page may combine multiple inventors who share the name “PENG CHAO-HSIEN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

PENG CHAO-HSIEN

TAIWAN SEMICONDUCTOR MFG

Method of semiconductor integrated circuit fabrication

Method for forming interconnect structure that avoids via recess

Lithography using multilayer spacer for reduced spacer footing

Interconnect structures comprising flexible buffer layers

Atomic layer deposition tantalum nitride layer to improve adhesion between a copper structure and overlying materials

Semiconductor device and fabrication method thereof

High performance metallization cap layer

Method of semiconductor integrated circuit fabrication

Method for forming recess-free interconnect structure

Sequential reducing plasma and inert plasma pre-treatment method for oxidizable conductor layer

Composite barrier layer

Method for forming a semiconductor device

Method for forming recess-free interconnect structure

Method of fabricating copper damascene

Method for forming composite barrier layer

TAIWAN SEMICONDUCTOR MFG CO LTD

Lithography using multilayer spacer for reduced spacer footing

Via pre-fill on back-end-of-the-line interconnect layer

Method of forming metal interconnection

Method for forming interconnect structure that avoids via recess

Interconnect structures comprising flexible buffer layers

Method of manufacturing a semiconductor device

Selective formation of conductor nanowires

Selective formation of conductor nanowires

Method of semiconductor integrated circuit fabrication

Via pre-fill on back-end-of-the-line interconnect layer

Selective formation of conductor nanowires

Method of semiconductor integrated circuit fabrication

Method of semiconductor integrated circuit fabrication

Method of semiconductor integrated circuit fabrication

Semiconductor device including liner structure