Inventor
CIVAY DENIZ E
US8 patents
Patents
8 patentsUS9754829B2Sep 5, 2017
Self-aligned conductive polymer pattern placement error compensation layer
GLOBALFOUNDRIES INC3 citations68
US10552567B2Feb 4, 2020
Automated redesign of integrated circuits using relaxed spacing rules
GLOBALFOUNDRIES INC2 citations64
US10186524B2Jan 22, 2019
Fully depleted silicon-on-insulator (FDSOI) transistor device and self-aligned active area in FDSOI bulk exposed regions
GLOBALFOUNDRIES INC0 citations50
US9941301B1Apr 10, 2018
Fully depleted silicon-on-insulator (FDSOI) transistor device and self-aligned active area in FDSOI bulk exposed regions
GLOBALFOUNDRIES INC0 citations50
US9397012B2Jul 19, 2016
Test pattern for feature cross-sectioning
GLOBALFOUNDRIES INC1 citations48
US9748176B2Aug 29, 2017
Pattern placement error compensation layer in via opening
GLOBALFOUNDRIES INC0 citations47
US9704807B2Jul 11, 2017
Pattern placement error compensation layer
GLOBALFOUNDRIES INC0 citations47
US9633942B1Apr 25, 2017
Conductively doped polymer pattern placement error compensation layer
GLOBALFOUNDRIES INC1 citations47