Inventor
CAREY SEAN M
US4 patents
Patents
4 patentsUS7676779B2Mar 9, 2010
Logic block timing estimation using conesize
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US7882472B2Feb 1, 2011
Method, apparatus, and computer program product for automatically waiving non-compute indications for a timing analysis process
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US10215804B2Feb 26, 2019
Semiconductor power and performance optimization
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US10372851B2Aug 6, 2019
Independently projecting a canonical clock
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