Inventor

WALKER WILLIAM L

US30 patents

⚠️ This page may combine multiple inventors who share the name “WALKER WILLIAM L”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

WALKER WILLIAM L

ADVANCED MICRO DEVICES INC

Processor-guided execution of offloaded instructions using fixed function operations

Processor-guided execution of offloaded instructions using fixed function operations

Shadow tag memory to monitor state of cachelines at different cache level

Systems and method for delayed cache utilization

Dynamic multithreaded cache allocation

Memory request throttling to constrain memory bandwidth utilization

Retaining cache entries of a processor core during a powered-down state

Coherency directory entry allocation based on eviction costs

Reducing cache footprint in cache coherence directory

Ring transport employing clock wake suppression

Memory request throttling to constrain memory bandwidth utilization

Rinsing cache lines from a common memory page to memory

Systems and method for delayed cache utilization

Retaining cache entries of a processor core during a powered-down state

Remote acceleration for data dependent address calculation

Re-fetching data for L3 cache data evictions into a last-level cache

Expandable buffer for memory transactions

Method and apparatus for storing a processor architectural state in cache memory

Accelerated cache rinse when preparing a power state transition

Cache resizing based on processor workload

I/O writes with cache steering

Method and apparatus for performing a bus lock and translation lookaside buffer invalidation

WALKER WILLIAM L

Dynamic multithreaded cache allocation

Method and apparatus for bypassing silicon bugs

Concurrent access to cache dirty bits

Method and apparatus for allocating instruction and data for a unified cache

HEWLETT PACKARD CO

Floating point operaton throughput control

Simultaneous execution of two memory reference instructions with only one address calculation

COMPAQ COMPUTER CORP

Error correction codes

KITCHIN PAUL

Power management of multiple compute units sharing a cache