Inventor

HEWITT LARRY D

US53 patents

⚠️ This page may combine multiple inventors who share the name “HEWITT LARRY D”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

HEWITT LARRY D

ADVANCED MICRO DEVICES INC

Circuit and method for maintaining order of memory access requests initiated by devices coupled to a multiprocessor system

Message based power management in a multi-processor system

Message based power management

Circuit and method for maintaining order of memory access requests initiated by devices in a multiprocessor system

Monolithic PC audio circuit with enhanced digital wavetable audio synthesizer

Charge dissipation in capacitively loaded ports

System including a host connected to a plurality of memory modules via a serial memory interconnect

Enhanced register array accessible by both a system microprocessor and a wavetable audio synthesizer

Bus arbiter including programmable request latency counters for varying arbitration priority

Use of a signal line to adjust width and/or frequency of a communication link during system operation

Computer resource configuration mechanism across a multi-pipe communication link

Integrated CPU and memory controller utilizing a communication link having isochronous and asynchronous priority modes

System and method for equalizing data buffer storage and fetch rates of peripheral devices

Wavetable audio synthesizer with low frequency oscillators for tremolo and vibrato effects

Method and apparatus for temperature sensing in integrated circuits

Serial interface having a read temperature command

Power control of circuit modules within an integrated circuit

Guaranteed edge synchronization for multiple clocks

Computer system including a bus bridge for connection to a security services processor

Configuring a communication link interface

Guaranteed data synchronization

Computer system implementing a system and method for ordering input/output (IO) memory operations within a coherent portion thereof

Input/output integrated circuit hub incorporating a RAMDAC

Staging buffer for translating clock domains when source clock frequency exceeds target clock frequency

Write only bus with whole and half bus mode operation

Communication link with isochronous and asynchronous priority modes

Computer system using signal modulation techniques to enhance multimedia device communication

PC audio system with frequency compensated wavetable data

PC audio system with wavetable cache

Method and apparatus for combined transaction reordering and buffer management

Computer interconnection bus link layer

Voltage regulators for an integrated circuit chip

System and method of assigning device numbers to I/O nodes of a computer system

System and method for analyzing bus transactions

Multimedia devices in computer system that selectively employ a communications protocol by determining the presence of the quaternary interface

Power management in a communication link

I/O node for a computer system including an integrated graphics engine

Peripheral interface circuit for an I/O node of a computer system

I/O node for a computer system including an integrated I/O interface

Variable frequency clock generation circuit using aperiodic patterns

Audio processing chip with external serial port

I/O node for a computer system including an integrated graphics engine and an integrated I/O hub

Dynamic reliability quality monitoring

External loopback test mode

Method and apparatus for coordinating combinatorial logic-clocked state machines

Technique for negotiating a width of a packet-based communication link

Electrical design current throttling

Computer system I/O node for connection serially in a chain to a host

LEGERITY INC

Monolithic PC audio circuit

SAF HOLLAND INC

Automated trailer coupling arrangement