Inventor

WU SHYE-LIN

TW212 patents

⚠️ This page may combine multiple inventors who share the name “WU SHYE-LIN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

WU SHYE-LIN

TEXAS INSTR ACER INC

Planarized deep-shallow trench isolation for CMOS/bipolar devices

Low mask count self-aligned silicided CMOS transistors with a high electrostatic discharge resistance

Method of fabricating deep-shallow trench isolation

Method of manufacturing deep sub-micron CMOS transistors

Method to fabricate dual threshold CMOS circuits

Method to form ultra-short channel MOSFET with a gate-side airgap structure

MOSFETs with recessed self-aligned silicide gradual S/D junction

Reduced mask CMOS salicided process

Fipos method of forming SOI CMOS structure

Method of fabricating CMOS transistors with self-aligned planarization twin-well by using fewer mask counts

Self-aligned silicided MOSFETS with a graded S/D junction and gate-side air-gap structure

Method to form shallow trench isolation with an oxynitride buffer layer

Method of manufacturing a multiple fin-shaped capacitor for high density DRAMs

Method to simulataneously fabricate the self-aligned silicided devices and ESD protective devices

Ultra-short channel elevated S/D MOSFETS formed on an ultra-thin SOI substrate

Process to fabricate the non-silicide region for electrostatic discharge protection circuit

MOSFET with self-aligned silicidation and gate-side air-gap structure

Method to form stacked-Si gate pMOSFETs with elevated and extended S/D junction

MOSFET with a high permitivity gate dielectric

Method to form mosfet with an inverse T-shaped air-gap gate structure

Method of making deep sub-micron meter MOSFET with a high permitivity gate dielectric

Method of forming MOSFET with buried contact and air-gap gate structure

Method for fabricating ultra short channel PMOSFET with buried source/drain junctions and self-aligned silicide

Method of forming high density and low power flash memories with a high capacitive-coupling ratio

High density flash memories with high capacitive-couping ratio and high speed operation

Method for forming MOSFET with an elevated source/drain

DRAM cell with a fork-shaped capacitor

Method to form MOSFET with an elevated source/drain

TAIWAN SEMICONDUCTOR MFG

Method of forming an N channel and P channel FINFET device on the same semiconductor substrate

Method of forming an N channel and P channel finfet device on the same semiconductor substrate

Method of fabricating three dimensional CMOSFET devices for an embedded DRAM application

Method for forming trench isolation regions

ACER SEMICONDUCTOR MANUFACTURI

Method of fabricating a self-aligned crown-shaped capacitor for high density DRAM cells

High density flat cell mask ROM

Method of forming a multiple fin-pillar capacitor for a high density dram cell

Method of forming a T-gate Lightly-Doped Drain semiconductor device

POWERCHIP SEMICONDUCTOR CORP

Method of fabricating a MOS device having a gate-side air-gap structure

Method for fabricating trench-isolation structure

Method of fabricating a short-channel MOS device

Process for forming shallow trench isolation

(unassigned)

Method of fabricating double poly-gate high density multi-state flat mask ROM cells

Method of forming high density flash memories with MIM structure

Method for fabricating MOSFETs with a recessed self-aligned silicide contact and extended source/drain junctions

Method to fabricate short-channel MOSFETs with an improvement in ESD resistance

VANGUARD INT SEMICONDUCT CORP

Method to form a capacitor having multiple pillars for advanced DRAMS

Tungsten silicide polycide gate electrode formed through stacked amorphous silicon (SAS) multi-layer structure.

Method for forming inverse-T gate lightly-doped drain (ITLDD) device

ACER SEMICONDUCTOR MFG INC

Method for fabricating high-density and high-speed nand-type mask roms

NAT SCIENCE COUNCIL

Method of fabricating a textured tunnel oxide for EEPROM applications

ACER SEMICONDUCTOR MFG CORP

Method for fabricating MOSFETS with a recessed self-aligned silicide contact and extended source/drain junctions