P

Inventor

GREASON JEFFREY K

US25 patents
⚠️ This page may combine multiple inventors who share the name “GREASON JEFFREY K”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

INTEL CORP

20 patents
US6448168B1Sep 10, 2002

Method for distributing a clock on the silicon backside of an integrated circuit

INTEL CORP382 citations99
US5412349AMay 2, 1995

PLL clock generator integrated with microprocessor

INTEL CORP123 citations98
US6037822AMar 14, 2000

Method and apparatus for distributing a clock on the silicon backside of an integrated circuit

INTEL CORP71 citations96
US5734187AMar 31, 1998

Memory cell design with vertically stacked crossovers

INTEL CORP54 citations96
US6316981B1Nov 13, 2001

Signal distribution network on backside of substrate

INTEL CORP23 citations92
US5963060AOct 5, 1999

Latching sense amplifier

INTEL CORP28 citations92
US5904486AMay 18, 1999

Method for performing a circuit edit through the back side of an integrated circuit die

INTEL CORP17 citations92
US5304869AApr 19, 1994

BiCMOS digital amplifier

INTEL CORP47 citations92
US5264785ANov 23, 1993

Voltage-controlled resistance element with superior dynamic range

INTEL CORP21 citations92
US6085341AJul 4, 2000

Memory test mode for wordline resistive defects

INTEL CORP24 citations89
US5736870AApr 7, 1998

Method and apparatus for bi-directional bus driver

INTEL CORP40 citations87
US5939942AAug 17, 1999

High frequency input buffer

INTEL CORP18 citations84
US6150718ANov 21, 2000

Method and apparatus for performing a circuit edit through the back side of an integrated circuit die

INTEL CORP12 citations74
US5898610AApr 27, 1999

Method and apparatus for bit cell ground choking for improved memory write margin

INTEL CORP15 citations74
US5111077AMay 5, 1992

BiCMOS noninverting buffer and logic gates

INTEL CORP8 citations74
US5049765ASep 17, 1991

BiCMOS noninverting buffer and logic gates

INTEL CORP8 citations74
US5113096AMay 12, 1992

BiCMOS circuit

INTEL CORP13 citations73
US6341326B1Jan 22, 2002

Method and apparatus for data capture using latches, delays, parallelism, and synchronization

INTEL CORP12 citations72
US5781557AJul 14, 1998

Memory test mode for wordline resistive defects

INTEL CORP12 citations70
US5699307ADec 16, 1997

Method and apparatus for providing redundant memory in an integrated circuit utilizing a subarray shuffle replacement scheme

INTEL CORP8 citations66

XCOR AEROSPACE

5 patents