Inventor

ZIEGLER MICHAEL L

US41 patents

⚠️ This page may combine multiple inventors who share the name “ZIEGLER MICHAEL L”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

ZIEGLER MICHAEL L

HEWLETT PACKARD CO

Partial cache line write transactions in a computing system with a write back cache

Multiprocessor system for maintaining cache coherency by checking the coherency in the order of the transactions being issued on the bus

Access hints for input/output address translation mechanisms

Computer apparatus having special instructions to force ordered load and store operations

Cache tag system for use with multiple processors including the most recently requested processor identification

Queue-based predictive flow control mechanism with indirect determination of queue fullness

Queue-based predictive flow control mechanism

Multiple arbitration scheme

System and method for dynamically updating memory address mappings

Coherence index generation for use by an input/output adapter located outside of the processor to detect whether the updated version of data resides within the cache

Translation mechanism for input/output addresses

Fast pipelined distributed arbitration scheme

HEWLETT PACKARD DEVELOPMENT CO

Compiler-based checkpointing for support of error recovery

Method and apparatus for resuming execution of a failed computer program

System and method for preloading cache memory in response to an occurrence of a context switch

Method and apparatus for varying the level of correctness checks executed when performing correctness checks opportunistically using spare instruction slots

Method for allowing distributed high performance coherent memory with full error containment

Program control flow conditioned on presence of requested data in cache memory

Processing element having dual control stores to minimize branch latency

Routing communications to a storage area network

Method for allowing distributed high performance coherent memory with full error containment

ZIEGLER MICHAEL L

Consistency checking for credit-based control of data communications

Packet descriptor trace indicators

Corrective actions based on probabilities

Delay queues based on delay remaining

Delays based on packet sizes

Target issue intervals

Node interface indicators

Indicators for streams associated with messages

Sending request messages to nodes indicated as unresolved

DATA GENERAL CORP

Data processing system

Universal memory

Data processing system having a unique instruction processor system

Data processing system having unique bus control protocol

Dual port cache with interleaved read accesses during alternate half-cycles and simultaneous writing

ALLIANT COMPUTER SYSTEMS

Digital computer with cache capable of concurrently handling multiple accesses from parallel processors

Computer with multiple processors having varying priorities for access to a multi-element memory

Digital computer with multisection cache

INTEL CORP

Method and apparatus for transferring data in a computer system

INST THE DEV OF EMERGING ARCHI

Apparatus and method for a load bias--load with intent to semaphore

TRAUB STEVEN

Reassembly of mini-packets in a buffer