Inventor
KELLER BRION L
US12 patents
⚠️ This page may combine multiple inventors who share the name “KELLER BRION L”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
IBM
6 patentsUS6986090B2Jan 10, 2006
Method for reducing switching activity during a scan operation with limited impact on the test coverage of an integrated circuit
IBM27 citations92
US5546408AAug 13, 1996
Hierarchical pattern faults for describing logic circuit failure mechanisms
IBM34 citations92
US6708305B1Mar 16, 2004
Deterministic random LBIST
IBM29 citations90
US7435990B2Oct 14, 2008
Arrangement for testing semiconductor chips while incorporated on a semiconductor wafer
IBM7 citations72
US7381986B2Jun 3, 2008
Arrangement for testing semiconductor chips while incorporated on a semiconductor wafer
IBM6 citations69
US6804803B2Oct 12, 2004
Method for testing integrated logic circuits
IBM5 citations61
CADENCE DESIGN SYSTEMS INC
5 patentsUS7693676B1Apr 6, 2010
Low power scan test for integrated circuits
CADENCE DESIGN SYSTEMS INC24 citations92
US9404969B1Aug 2, 2016
Method and apparatus for efficient hierarchical chip testing and diagnostics with support for partially bad dies
CADENCE DESIGN SYSTEMS INC25 citations91
US6782501B2Aug 24, 2004
System for reducing test data volume in the testing of logic products
CADENCE DESIGN SYSTEMS INC34 citations89
US9864004B1Jan 9, 2018
System and method for diagnosing failure locations in electronic circuits
CADENCE DESIGN SYSTEMS INC8 citations81
US7103816B2Sep 5, 2006
Method and system for reducing test data volume in the testing of logic products
CADENCE DESIGN SYSTEMS INC4 citations60