Inventor
EARL JEFFREY S
US18 patents
⚠️ This page may combine multiple inventors who share the name “EARL JEFFREY S”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
VANGUARD INT SEMICONDUCT CORP
7 patentsUS6064226AMay 16, 2000
Multiple input/output level interface input receiver
VANGUARD INT SEMICONDUCT CORP57 citations95
US6246619B1Jun 12, 2001
Self-refresh test time reduction scheme
VANGUARD INT SEMICONDUCT CORP57 citations93
US6060873AMay 9, 2000
On-chip-generated supply voltage regulator with power-up mode
VANGUARD INT SEMICONDUCT CORP11 citations74
US6330203B1Dec 11, 2001
Test mode for verification of on-chip generated row addresses
VANGUARD INT SEMICONDUCT CORP7 citations73
US5973895AOct 26, 1999
Method and circuit for disabling a two-phase charge pump
VANGUARD INT SEMICONDUCT CORP7 citations73
US6040719AMar 21, 2000
Input receiver for limiting current during reliability screening
VANGUARD INT SEMICONDUCT CORP6 citations62
US6764867B1Jul 20, 2004
Reticle option layer detection method
VANGUARD INT SEMICONDUCT CORP5 citations61
AVAGO TECH INT SALES PTE LID
6 patentsUS11947472B2Apr 2, 2024
Composable infrastructure enabled by heterogeneous architecture, delivered by CXL based cached switch SoC
AVAGO TECH INT SALES PTE LID3 citations85
US12386751B2Aug 12, 2025
Composable infrastructure enabled by heterogeneous architecture, delivered by CXL based cached switch SOC and extensible via cxloverethernet (COE) protocols
AVAGO TECH INT SALES PTE LID0 citations62
US12360937B2Jul 15, 2025
Compute express Link™ (CXL) over ethernet (COE)
AVAGO TECH INT SALES PTE LID0 citations62
US12326813B2Jun 10, 2025
Heterogeneous architecture, delivered by cxl based cached switch SOC and extensible via cxloverethernet (COE) protocols
AVAGO TECH INT SALES PTE LID0 citations62
US12259816B2Mar 25, 2025
Composable infrastructure enabled by heterogeneous architecture, delivered by CXL based cached switch SOC
AVAGO TECH INT SALES PTE LID0 citations62
US11989143B2May 21, 2024
Composable infrastructure enabled by heterogeneous architecture, delivered by CXL based cached switch SoC
AVAGO TECH INT SALES PTE LID0 citations62
CADENCE DESIGN SYSTEMS INC
3 patentsUS10642538B1May 5, 2020
Multi-channel memory interface
CADENCE DESIGN SYSTEMS INC19 citations85
US8760210B1Jun 24, 2014
Multiple samples with delay in oversampling in phase
CADENCE DESIGN SYSTEMS INC0 citations51
US10885952B1Jan 5, 2021
Memory data transfer and switching sequence
CADENCE DESIGN SYSTEMS INC0 citations46